Theres the open source Digital (https://github.com/hneemann/Digital https://github.com/hneemann/Digital) which can run simulations but then export Verilog. If

Theres the open source Digital (https://github.com/hneemann/Digital https://github.com/hneemann/Digital) which can run simulations but then export Verilog. If you have an ICE40 based GPU then in theory you can then use open source tools (like apio) to get that onto your FPGA. I've seen some impressive fpga tasks being generated by that. I'm early in my learning of FPGA and have done nandgame and some other non-HDL circuit learnings. I have gone back and forth if I want to design my project via HDL or via something like Digital. There's not an easy pro/con either way. For example, everything I've read is that the verilog block diagram tools kinda create isn't behavior, which makes optimization by FPGA compilers hard, because it can't automatically infer optimal feature gate usage if you are giving transistor level HDL vs behavior HDL. Likewise, it's not totally clear if block diagramming tools can facilitate test bench behavior, which I think I want to prevent regressions.