4 ms·
In computer programming, you can get say a ~10x speed improvement between writing bit twiddling code in python and hand writing SIMD assembly to do the same job
by londons_explore 3y ago
In computer programming, you can get say a ~10x speed improvement between writing bit twiddling code in python and hand writing SIMD assembly to do the same job.
Is there a similar gaping gap between writing verilog for something, vs hand-designing the lookup tables and laying out the FPGA routing?
- sitkack 3y agoPython to SIMD is 1000x, to HDL it is 10k to 100k multiple. Python is 100x slower than native code. SIMD often gets you a 10x increase or more from native.
- nrclark 3y agoMost FPGAs have various kinds of primitives that can be instantiated manually in the middle of a larger Verilog design. Sometimes those primitives can be used to do things that are very hard to make the synthesizer create automatically. In general, the synthesizer will be better than you at anything lookup-table or flip-flop related. Ditto for simple primitives like shift-registers. But it probably doesn't know how to infer the more complicated primitives, and so those are usually done with the Verilog equivalent of inline assembly. For a few tight designs, I've given some hints to the the placer. These are things like grouping components together, or setting location constraints on a few key primitives. That kind of thing isn't too uncommon. I've never seen anybody try to route things manually though.