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> because the specification of SystemVerilog is too complicated Right, too big and complicated, too much stuff to decently cover in one language (more than e.g
by Rochus 3y ago
> because the specification of SystemVerilog is too complicated
Right, too big and complicated, too much stuff to decently cover in one language (more than e.g. Ada covers), and the majority of people use only a fraction of it (different identifiable user groups use different subsets).
Do you try to add the full SV feature set in your language, or do you focus on a user group/use-case?
- dalance 3y agoI'm focusing ASIC designers who write synthesizable SystemVerilog. So I choose language features to avoid mismatch between synthesis and simulation. Verification engineers is a second group. But verification features like SVA and UVM are too large. So I think it may be better to achieve these features by interoperation with SystemVerilog instead of adding them to Veryl.
- Rochus 3y agoI appreciated e.g. in Wirth's Lola-2 HDL that it was conceived up-front for synchronous design and you didn't waste hours to explain to people how to select the proper subset of the language for the most prevalent use-case. Concerning verification, I assume more and more people use other languages for verification than SV, e.g. Python or C++.
- dalance 3y agoThank you for your information about Lola-2 HDL. I'll check it. As a verification engineer, I write large verification models by Rust, and connect them to SV testbench through DPI. The same usage can be done by Veryl. About Python, cocotb integration seems to be good for integrated unit test feature. So I've just started to consider about the idea.