4 ms·
2nm, sure, but what about SRAM register files and caches? SRAM has pretty much stopped scaling already. SRAM scaling is where I'd love to see some advances.
by vardump 3y ago
2nm, sure, but what about SRAM register files and caches? SRAM has pretty much stopped scaling already.
SRAM scaling is where I'd love to see some advances.
- imtringued 3y agoWe need the same 3D stacking they do on NAND flash.
- xw390111 3y agoIt's getting denser, but just not as fast as logic. https://www.techpowerup.com/309331/tsmc-n3-nodes-show-sram-scaling-is-hitting-the-wall https://www.techpowerup.com/309331/tsmc-n3-nodes-show-sram-s... You can make them smaller (like 20%) but those SRAMs suck electrically so no product actually uses them. So in actually shipping products the SRAM is roughly the same size (like 5% smaller). One needs to remember these things are drawn by algorithms (no one is by hand drawing billions of transistors) and there have been 20 years+ of advancements on the algorithms that draw SRAM and because of the regularity of SRAM there's more opportunity to pack. There's just not that much fat to cut in a SRAM structure (that's purely optimizing for density) so in many ways SRAM structures are the true measure of how small things are, and they are in fact used that way. And things are really really tiny already.
- monocasa 3y agoThey went back to N5 SRAM sizes with N3E because of yield issues on N3B. https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-even https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-e...