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I think they meant fake as in "doesn't relate to any size of the transistors", as the gate/metal pitch sizes are e.g. 40 nm and 54 nm respectively for Intel's "
by tlamponi 3y ago
I think they meant fake as in "doesn't relate to any size of the transistors", as the gate/metal pitch sizes are e.g. 40 nm and 54 nm respectively for Intel's "7nm" node [0], even the fin pitch is 34 nm, so almost 5 times bigger than the marketing term would like to imply.
[0]: https://en.wikipedia.org/wiki/7_nm_process#Process_nodes_and_process_offerings https://en.wikipedia.org/wiki/7_nm_process#Process_nodes_and...
- TehCorwiz 3y agoAh, yeah. I can see that. So what does that refer to then, the smallest size of any feature of the transistor?
- Hizonner 3y agoIt does not refer to the physical size of any element or feature of the chips. It's the marketing department's claim about what you'd have had to do to achieve "equivalent performance" using geometries (and probably other things) that are no longer used. Or to put it another way it's completely untethered from reality in every way.