3 ms·
Seems interesting - if I understand, this lets you get Verilog from a frontend you build. Can this be used to implement say a backend for pytorch? How does one
by buildbot 3y ago
Seems interesting - if I understand, this lets you get Verilog from a frontend you build. Can this be used to implement say a backend for pytorch? How does one link the generated verilog to software that can drive the design (in sim or actual FPGA/ASIC hardware)?
Or is that left to you to build a driver separately for?
- rachitnigam 3y agoAuthor of Calyx here. Good question! Usually, you can use OpenCL based drivers to interface with standard memory interfaces on FPGAs. ASICs require a lot more work by either packaging on the same chip as a processor or building IO interfaces for their own package.