6 ms·

RISC-V Assembler: Arithmetic

72 points by WillFlux 3y ago

WillFlux 3y ago
68000 is, in many ways, the pinnacle of assembler for programming, but RISC-V is pretty fun, too. I hope RISC-V tempts a few more people to try asm programming (again).
- snvzz 3y ago
  I got into 68000 programming quite late (6yr ago), but I have been enjoying it (so far Amiga, Atari ST, rosco-m68k). It is a very programmer-friendly instruction set architecture. RISC-V I started playing with more recently (early 2023, thanks to VisionFive 2), and it feels like my old favorite (MIPS), without the baggage MIPS carried. It is a pleasure to work with this amount of GPRs and the comfortable alternative names for them that the official abi offers. I am loving it so far. I expect to have RVA22+V hardware soon (Milk-V Oasis). Very much looking forward to playing with the vector extension on that.
  - sylware 3y ago
    Yep, same, I am keeping an eye on Oasis, but to run powerful GPU drivers (much user space would have to be ported from c++ to hand written risc-v assembly, SDK included). Don't rush it though, concurrent access and memory coherence of device memory is still not finalized. I have been coding kind of a lot x64 recently, the limitation of 16 GPRs has been painful. I am sure that when I will crank up on rv64 assembly programming, those 32GPRs will feel like fresh air. In the other hand, I am not fond of the ABI register names, and the pseudo-instructions involving mini-compilation. I'll stick to xNUMBER register names and won't use pseudo-instructions. Like I will avoid any abuse of the preprocessor.
    - snvzz 3y ago
      >In the other hand, I am not fond of the ABI register names Why? They're simple substitution, and very helpful with following ABI. >and the pseudo-instructions involving mini-compilation. Again, why? These aren't specific to the assembler used, but rather, defined in the specification itself. This means they are reliable, and will always be there for as long as you use a RISC-V compliant assembler. They are thus also the register names you will see in disassembler output, debuggers and other tools. Also, you might be interested in this new RVA22+V board[0]. 0. https://forum.banana-pi.org/t/leading-the-future-of-computing-power-banana-pi-bpi-f3-risc-v-development-board/17202 https://forum.banana-pi.org/t/leading-the-future-of-computin...
      - Findecanor 3y ago
        The standard pseudo-instructions are not just standard. They express idioms that get treated differently, sometimes also by hardware. For example `li` gets expanded by the assembler into `liu` and `addi` which on larger RISC-V cores get recognised and fused back into a single op. Using `xori` instead of `addi` would have had the same result but wouldn't get fused. Next, some idioms get recognised and automatically assembled into "compressed" 16-bit instructions to save space. For example "mv rd,rs" and "addi rd, rs, 0" both get assembled into "c.mv rd,rs". And on a larger RISC-V core, "c.mv" could be only a register rename in the decoder, thus taking 0 cycles.
throwaway71271 3y ago
I love RISC-V assembler. I did a bit of x86 as stuff 20 years ago but hated it, now I wanted to teach my daughter some c and assembler and was thinking between arm and riscv, but riscv is just a joy to teach (I made a riscv assembler boardgame to help with the task https://punkx.org/overflow/ https://punkx.org/overflow/) Recently I was rewatching Hackers(1995) and I also got excited about the same quote: > “RISC architecture is going to change everything.” — Acid Burn After spending some time with esp32s and riscv assembler, I think its more true than before :) If you havent given it a try yet, there are many articles like the one, and also projects like https://luplab.gitlab.io/rvcodecjs/ https://luplab.gitlab.io/rvcodecjs/ or https://riscv.vercel.app/ https://riscv.vercel.app/ where you can play with it, or even make your own emulator by learning from other emulators like https://github.com/OpenMachine-ai/tinyfive/blob/main/machine.py https://github.com/OpenMachine-ai/tinyfive/blob/main/machine... this cheatsheet is also very useful: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...
- stockhorn 3y ago
  Wow... Crazy this boardgame of yours. I'll definitly take a deeper look at this :). Thanks
  - throwaway71271 3y ago
    thanks!
- snvzz 3y ago
  Note this is an older (pre-ratification) cheatsheet. You can tell because sbreak/scall. They are ebreak/ecall in the final version. AIUI, the reason the name was changed is that they're not necessarily calls to the supervisor. E.g. they could be calls to machine mode, or the hypervisor. And some chips only implement M mode.
sylware 3y ago
RISC-V, being an ISA worldwide royalty free standard, is meant for assembly writting. The main reason, above the "comfort" reason of C and similar, was ISA abstraction which has no meaning in the RISC-V realm. The middle ground is those very high level language interpreters (python/lua/ruby/javascript/etc) written directly in RISC-V assembly (without abuse of any assembler preprocessor, ofc). I am currently writting my own rv64 on x64 virtual machine process, to code my programs in rv64 and not anymore in x64 in order to be "real hardware ready". BTW, anybody knows a EU based distributor of milk-v duo boards with the cv1800 SOC (the one without ARM cores and a rv64 MCU) which I can contact using my domestic email server?
IshKebab 3y ago
> ProTip: Hexadecimal literals are prefixed with 0x. I love the idea that someone could get to this page and not already know that! Also this nicely highlights my pet peeve with assembly: add rd, rs1, rs2 # rd = rs1 + rs2 It's very difficult to remember which parameter is the destination etc. IMO it would be much nicer if assembly had just a little more syntax for that sort of thing. E.g. rd = add rs1, rs2 t0 = li 5 Just so the destination register is obvious. Ah well, nobody's going to do that. Assembly parsing is a total mess; there's no official grammar or anything - it's just "what GCC/LLVM do".
- Findecanor 3y ago
  > I love the idea that someone could get to this page and not already know that! Might be worth noting because it is different in other assembly languages. In e.g. 6502 and MC680x0 asm, you'd first prefix with # to differentiate between an address (to load from and/or store to) and an "immediate" constant number, and then $ to denote hexadecimal. In x86 assembly (Intel style), you instead suffix the number with the letter h. > rd = add rs1, rs2 There are assembly languages for a few architectures that did/have that form or a similar one. Itanium assembly had instead the form: add r1 = r2, r3
- JAlexoid 3y ago
  Assembly is a language, that can be extended. Assembly++? But at some point doing simple C makes more sense, than adding syntactic sugar to Assembly.
- epcoa 3y ago
  > there's no official grammar Most architectures have something. Sparc had one (I still have the manual), PPC, 68k. I would even say x86 does as well but you can’t force its adoption, what AT&T and GNU wants to do on their own can’t be prevented. AT&T I suppose had the goal of making it all consistent, but I’m not sure if that was an improvement. Though I know of its vocal defendants. RISC-V might be the exception more than anything, but they have a defacto syntax used throughout the spec. Analog Devices DSPs and Itanium are examples with the = token. http://laplace.physics.ubc.ca/vnp4/intel/docs/asm_lan.pdf http://laplace.physics.ubc.ca/vnp4/intel/docs/asm_lan.pdf https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf

72 points by WillFlux 3y ago

68000 is, in many ways, the pinnacle of assembler for programming, but RISC-V is pretty fun, too. I hope RISC-V tempts a few more people to try asm programming (again).

snvzz 3y ago
I got into 68000 programming quite late (6yr ago), but I have been enjoying it (so far Amiga, Atari ST, rosco-m68k). It is a very programmer-friendly instruction set architecture. RISC-V I started playing with more recently (early 2023, thanks to VisionFive 2), and it feels like my old favorite (MIPS), without the baggage MIPS carried. It is a pleasure to work with this amount of GPRs and the comfortable alternative names for them that the official abi offers. I am loving it so far. I expect to have RVA22+V hardware soon (Milk-V Oasis). Very much looking forward to playing with the vector extension on that.
- sylware 3y ago
  Yep, same, I am keeping an eye on Oasis, but to run powerful GPU drivers (much user space would have to be ported from c++ to hand written risc-v assembly, SDK included). Don't rush it though, concurrent access and memory coherence of device memory is still not finalized. I have been coding kind of a lot x64 recently, the limitation of 16 GPRs has been painful. I am sure that when I will crank up on rv64 assembly programming, those 32GPRs will feel like fresh air. In the other hand, I am not fond of the ABI register names, and the pseudo-instructions involving mini-compilation. I'll stick to xNUMBER register names and won't use pseudo-instructions. Like I will avoid any abuse of the preprocessor.
  - snvzz 3y ago
    >In the other hand, I am not fond of the ABI register names Why? They're simple substitution, and very helpful with following ABI. >and the pseudo-instructions involving mini-compilation. Again, why? These aren't specific to the assembler used, but rather, defined in the specification itself. This means they are reliable, and will always be there for as long as you use a RISC-V compliant assembler. They are thus also the register names you will see in disassembler output, debuggers and other tools. Also, you might be interested in this new RVA22+V board[0]. 0. https://forum.banana-pi.org/t/leading-the-future-of-computing-power-banana-pi-bpi-f3-risc-v-development-board/17202 https://forum.banana-pi.org/t/leading-the-future-of-computin...
    - Findecanor 3y ago
      The standard pseudo-instructions are not just standard. They express idioms that get treated differently, sometimes also by hardware. For example `li` gets expanded by the assembler into `liu` and `addi` which on larger RISC-V cores get recognised and fused back into a single op. Using `xori` instead of `addi` would have had the same result but wouldn't get fused. Next, some idioms get recognised and automatically assembled into "compressed" 16-bit instructions to save space. For example "mv rd,rs" and "addi rd, rs, 0" both get assembled into "c.mv rd,rs". And on a larger RISC-V core, "c.mv" could be only a register rename in the decoder, thus taking 0 cycles.

throwaway71271 3y ago

I love RISC-V assembler. I did a bit of x86 as stuff 20 years ago but hated it, now I wanted to teach my daughter some c and assembler and was thinking between arm and riscv, but riscv is just a joy to teach (I made a riscv assembler boardgame to help with the task https://punkx.org/overflow/ https://punkx.org/overflow/) Recently I was rewatching Hackers(1995) and I also got excited about the same quote: > “RISC architecture is going to change everything.” — Acid Burn After spending some time with esp32s and riscv assembler, I think its more true than before :) If you havent given it a try yet, there are many articles like the one, and also projects like https://luplab.gitlab.io/rvcodecjs/ https://luplab.gitlab.io/rvcodecjs/ or https://riscv.vercel.app/ https://riscv.vercel.app/ where you can play with it, or even make your own emulator by learning from other emulators like https://github.com/OpenMachine-ai/tinyfive/blob/main/machine.py https://github.com/OpenMachine-ai/tinyfive/blob/main/machine... this cheatsheet is also very useful: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...

stockhorn 3y ago
Wow... Crazy this boardgame of yours. I'll definitly take a deeper look at this :). Thanks
- throwaway71271 3y ago
  thanks!
snvzz 3y ago
Note this is an older (pre-ratification) cheatsheet. You can tell because sbreak/scall. They are ebreak/ecall in the final version. AIUI, the reason the name was changed is that they're not necessarily calls to the supervisor. E.g. they could be calls to machine mode, or the hypervisor. And some chips only implement M mode.

sylware 3y ago

RISC-V, being an ISA worldwide royalty free standard, is meant for assembly writting. The main reason, above the "comfort" reason of C and similar, was ISA abstraction which has no meaning in the RISC-V realm. The middle ground is those very high level language interpreters (python/lua/ruby/javascript/etc) written directly in RISC-V assembly (without abuse of any assembler preprocessor, ofc). I am currently writting my own rv64 on x64 virtual machine process, to code my programs in rv64 and not anymore in x64 in order to be "real hardware ready". BTW, anybody knows a EU based distributor of milk-v duo boards with the cv1800 SOC (the one without ARM cores and a rv64 MCU) which I can contact using my domestic email server?

IshKebab 3y ago

> ProTip: Hexadecimal literals are prefixed with 0x. I love the idea that someone could get to this page and not already know that! Also this nicely highlights my pet peeve with assembly: add rd, rs1, rs2 # rd = rs1 + rs2 It's very difficult to remember which parameter is the destination etc. IMO it would be much nicer if assembly had just a little more syntax for that sort of thing. E.g. rd = add rs1, rs2 t0 = li 5 Just so the destination register is obvious. Ah well, nobody's going to do that. Assembly parsing is a total mess; there's no official grammar or anything - it's just "what GCC/LLVM do".

Findecanor 3y ago
> I love the idea that someone could get to this page and not already know that! Might be worth noting because it is different in other assembly languages. In e.g. 6502 and MC680x0 asm, you'd first prefix with # to differentiate between an address (to load from and/or store to) and an "immediate" constant number, and then $ to denote hexadecimal. In x86 assembly (Intel style), you instead suffix the number with the letter h. > rd = add rs1, rs2 There are assembly languages for a few architectures that did/have that form or a similar one. Itanium assembly had instead the form: add r1 = r2, r3
JAlexoid 3y ago
Assembly is a language, that can be extended. Assembly++? But at some point doing simple C makes more sense, than adding syntactic sugar to Assembly.
epcoa 3y ago
> there's no official grammar Most architectures have something. Sparc had one (I still have the manual), PPC, 68k. I would even say x86 does as well but you can’t force its adoption, what AT&T and GNU wants to do on their own can’t be prevented. AT&T I suppose had the goal of making it all consistent, but I’m not sure if that was an improvement. Though I know of its vocal defendants. RISC-V might be the exception more than anything, but they have a defacto syntax used throughout the spec. Analog Devices DSPs and Itanium are examples with the = token. http://laplace.physics.ubc.ca/vnp4/intel/docs/asm_lan.pdf http://laplace.physics.ubc.ca/vnp4/intel/docs/asm_lan.pdf https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf