4 ms·

Since nm are Now Marketing, unrelated to physical dimension, how consequential is this node shrink? It must have passed some threshold to justify new factories

Since nm are Now Marketing, unrelated to physical dimension, how consequential is this node shrink? It must have passed some threshold to justify new factories - what was it?

nightski 3y ago
Would it make a difference if it was physical dimension? Wouldn't you simply be asking the same question?
ip26 3y ago
I have no inside information, but gate-all-around and backside power are both pretty big developments. If you remember the rise of finfet, gate-all-around will probably be a similar step up (maybe slightly smaller). My guess is backside power is the less impactful of the two, and a little less directly quantifiable, but for route-limited designs it should enable 10-20% higher density which reduces cost and improves performance. It may also deliver higher quality power supplies, which improves power efficiency and maximum clock frequency. It's hard to directly answer "how consequential", but it seems like it could be as significant as the step to TSMC 16nm.
- samstave 3y ago
  [flagged]
  - zozbot234 3y ago
    Good parrot. But how do I know that it didn't make some of that up?
    - samstave 3y ago
      It might take an electron microscope to see exactly whats going on
prng2021 3y ago
"In July 2022, TSMC announced that its N2 process technology will feature backside power delivery and will offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E" https://en.m.wikipedia.org/wiki/2_nm_process https://en.m.wikipedia.org/wiki/2_nm_process
audunw 3y ago
> Since nm are Now Marketing, unrelated to physical dimension That's not entirely true. They might not decrease the minimum gate length, but generally the improvements made when bumping down the "nm" number has been a similar improvement as what making the gate length smaller would have given. So I don't find the numbering as misleading as others think. It's not like any of us a designing gate cell libraries (well, I have, a very basic one, but I'm guessing most here haven't), and actually care about the gate length. Using the minimum gate length as a naming scheme was always been a proxy for things chip designers actually care about: logic density, timing, power, etc.
phatfish 3y ago
Marketing sure painted themselves into a corner on this one by counting backwards, they only have one generation left before things get weird. Will they use fractions or go negative?
- dontreact 3y ago
  Aren't there units smaller than nm?
  - hyperthesis 3y ago
    Yep, and they used to be measured in microns. e.g. the Z80 used the 4 μm process node https://wikipedia.org/wiki/Zilog_Z80 https://wikipedia.org/wiki/Zilog_Z80 1000nm = 1μm Next smallest is picometers, 1000pm = 1nm

Since nm are Now Marketing, unrelated to physical dimension, how consequential is this node shrink? It must have passed some threshold to justify new factories - what was it?

nightski 3y ago

Would it make a difference if it was physical dimension? Wouldn't you simply be asking the same question?

ip26 3y ago

I have no inside information, but gate-all-around and backside power are both pretty big developments. If you remember the rise of finfet, gate-all-around will probably be a similar step up (maybe slightly smaller). My guess is backside power is the less impactful of the two, and a little less directly quantifiable, but for route-limited designs it should enable 10-20% higher density which reduces cost and improves performance. It may also deliver higher quality power supplies, which improves power efficiency and maximum clock frequency. It's hard to directly answer "how consequential", but it seems like it could be as significant as the step to TSMC 16nm.

samstave 3y ago
[flagged]
- zozbot234 3y ago
  Good parrot. But how do I know that it didn't make some of that up?
  - samstave 3y ago
    It might take an electron microscope to see exactly whats going on

prng2021 3y ago

"In July 2022, TSMC announced that its N2 process technology will feature backside power delivery and will offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E" https://en.m.wikipedia.org/wiki/2_nm_process https://en.m.wikipedia.org/wiki/2_nm_process

audunw 3y ago

> Since nm are Now Marketing, unrelated to physical dimension That's not entirely true. They might not decrease the minimum gate length, but generally the improvements made when bumping down the "nm" number has been a similar improvement as what making the gate length smaller would have given. So I don't find the numbering as misleading as others think. It's not like any of us a designing gate cell libraries (well, I have, a very basic one, but I'm guessing most here haven't), and actually care about the gate length. Using the minimum gate length as a naming scheme was always been a proxy for things chip designers actually care about: logic density, timing, power, etc.

phatfish 3y ago

Marketing sure painted themselves into a corner on this one by counting backwards, they only have one generation left before things get weird. Will they use fractions or go negative?

dontreact 3y ago
Aren't there units smaller than nm?
- hyperthesis 3y ago
  Yep, and they used to be measured in microns. e.g. the Z80 used the 4 μm process node https://wikipedia.org/wiki/Zilog_Z80 https://wikipedia.org/wiki/Zilog_Z80 1000nm = 1μm Next smallest is picometers, 1000pm = 1nm