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> I haven't seen a solid defence for the lack of conditional move or advanced addressing modes either. That's backwards. It's the people who want those who nee

> I haven't seen a solid defence for the lack of conditional move or advanced addressing modes either. That's backwards. It's the people who want those who need to prove they make a significant difference, and not just with hand-waving but with actual chips and data. "Everyone else does it" is not data. Thus far, RISC-V cores come in very competitive and even faster than Arm cores with similar µarch e.g. SiFive U74 vs Arm A55, or THead C910 vs Arm A72. > the pain of compressed instructions is very very very high Only for people who bought a company with a fast Aarch64 core that Arm is suing them over using so are trying to convert it to be a RISC-V core instead, with minimal work. The companies that are designing fast and wide RISC-V cores from scratch (Ventana, Tenstorrent, Rivos, ...) are saying the C extension is no big deal to implement, and of course does have real advantages in static and dynamic code size, icache size / performance / bandwidth etc. The discussion you referenced has Qualcomm claiming Rivos is also against the C extension, and then a Rivos person coming back saying "Hang on just a minute ... we're fine with C, we're just open-minded enough to want to see real data on your proposal".

IshKebab 3y ago
> THead C910 This has an extensions that support conditional move and indexed memory access :-D See https://sourceware.org/binutils/docs/as/RISC_002dV_002dCustomExts.html https://sourceware.org/binutils/docs/as/RISC_002dV_002dCusto... In any case you aren't going to be able to see the benefit by comparing totally different cores. There are too many other factors. The article says: > Arm considered eliminating predicated execution entirely, but conditional move and a few other conditional instructions provided such a large performance win that Arm kept them. It would definitely be great to see numbers here but I see no reason to doubt that. > Only for people who bought a company with a fast Aarch64 core that Arm is suing them over using so are trying to convert it to be a RISC-V core instead, with minimal work. I'm not sure what you are talking about here. I was referring to the fact that the C extension means uncompressed instructions may not be naturally aligned which leads to all sorts of complexities, e.g. fetching instructions that are split over a page boundary, different PMA regions, different PMP regions, etc. It adds a lot of complexity to CHERI too. It's not a "big deal" to implement, but it does add significant complexity which would have been nice to avoid if it wasn't actually necessary.
- camel-cdr 3y ago
  > This has an extensions that support conditional move and indexed memory access :-D RISC-V has Zicond now.

IshKebab 3y ago

> THead C910 This has an extensions that support conditional move and indexed memory access :-D See https://sourceware.org/binutils/docs/as/RISC_002dV_002dCustomExts.html https://sourceware.org/binutils/docs/as/RISC_002dV_002dCusto... In any case you aren't going to be able to see the benefit by comparing totally different cores. There are too many other factors. The article says: > Arm considered eliminating predicated execution entirely, but conditional move and a few other conditional instructions provided such a large performance win that Arm kept them. It would definitely be great to see numbers here but I see no reason to doubt that. > Only for people who bought a company with a fast Aarch64 core that Arm is suing them over using so are trying to convert it to be a RISC-V core instead, with minimal work. I'm not sure what you are talking about here. I was referring to the fact that the C extension means uncompressed instructions may not be naturally aligned which leads to all sorts of complexities, e.g. fetching instructions that are split over a page boundary, different PMA regions, different PMP regions, etc. It adds a lot of complexity to CHERI too. It's not a "big deal" to implement, but it does add significant complexity which would have been nice to avoid if it wasn't actually necessary.

camel-cdr 3y ago
> This has an extensions that support conditional move and indexed memory access :-D RISC-V has Zicond now.