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Funny, I just started (yesterday!!) something similar: a kind of x86_64 (which I call x64) virtual machine for rv64. I am writting this "virtual machine" in x8

Funny, I just started (yesterday!!) something similar: a kind of x86_64 (which I call x64) virtual machine for rv64. I am writting this "virtual machine" in x86_64 assembly though (linux ABI). I don't plan to have native x86_64 compilation but only an interpreter. This idea is to code rv64 executables(linux) which I could "run-ish" on x86_64(linux). There is also the real machine emulator from M.Bellard : https://bellard.org/tinyemu https://bellard.org/tinyemu Well, RISC-V is gaining momentum, and transition apparatus from x86_64 is taking shaped from many individuals wishing risc-v to be a success. BTW, if anybody knows about milk-v duo (the one with the SOC free from arm cores) resellers in Europe I can pay without a credit card and I can contact with a self-hosted email... thank you.

sitkack 3y ago
That sounds exciting, please keep us posted.
- sylware 3y ago
  I will try to do it, but there is a huge trade-off: elf is gone.
  - sitkack 3y ago
    What do you mean by elf is gone? You might be able to use this, https://github.com/cole14/rust-elf/ https://github.com/cole14/rust-elf/
    - sylware 3y ago
      I did remove elf period, I use a 'json/wayland' like format, namely excrutiatingly simple for modern CPUs. Additionnaly, there is no rust anything here, or any other compiler based language, it is assembly, x86_64 and risc-v assembly (I even use a x86_64 intel syntax which does assemble on 4 assemblers). I had the time to start to think how to do that, I was hit hard by the LR/SC emulation/interpretation issue. Those LR/SC pairs are extremely dangerous and can livelock easily, and understanding the theorical puzzle of the specs which seems to try to fix that is meh (it must be extremely rigorous on the theorical prerequisites for this very, as this is so much critical and does not seem to be): "the eventual success of store-conditional instructions". The theorical puzzle I am trying to figure out seems to miss a rigorous definition of the "failing of store-conditional instructions". In the end, it seems proper emulation on x86_64 will be very slow as each store/load will have to go thru some expensive code in order to deal with lr/sc. But that's fine, as I am more interested in running correctly risc-v code than omega quickly (intel and amd have nastily failed at providing lr/sc semantics hardware instructions to x86_64, see the Intel TSX debacle). I may implement a full virtual memory controller, significant performance penalty will happen for the sake of correctness.

sitkack 3y ago

That sounds exciting, please keep us posted.

sylware 3y ago
I will try to do it, but there is a huge trade-off: elf is gone.
- sitkack 3y ago
  What do you mean by elf is gone? You might be able to use this, https://github.com/cole14/rust-elf/ https://github.com/cole14/rust-elf/
  - sylware 3y ago
    I did remove elf period, I use a 'json/wayland' like format, namely excrutiatingly simple for modern CPUs. Additionnaly, there is no rust anything here, or any other compiler based language, it is assembly, x86_64 and risc-v assembly (I even use a x86_64 intel syntax which does assemble on 4 assemblers). I had the time to start to think how to do that, I was hit hard by the LR/SC emulation/interpretation issue. Those LR/SC pairs are extremely dangerous and can livelock easily, and understanding the theorical puzzle of the specs which seems to try to fix that is meh (it must be extremely rigorous on the theorical prerequisites for this very, as this is so much critical and does not seem to be): "the eventual success of store-conditional instructions". The theorical puzzle I am trying to figure out seems to miss a rigorous definition of the "failing of store-conditional instructions". In the end, it seems proper emulation on x86_64 will be very slow as each store/load will have to go thru some expensive code in order to deal with lr/sc. But that's fine, as I am more interested in running correctly risc-v code than omega quickly (intel and amd have nastily failed at providing lr/sc semantics hardware instructions to x86_64, see the Intel TSX debacle). I may implement a full virtual memory controller, significant performance penalty will happen for the sake of correctness.