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AMD proposes an FPGA subsystem user-space interface for Linux
- gen3 3y agoI think this would be a really cool feature. Imagine editing video and being able to add an updated h265 encoder
- buildbot 3y agoThere is something kinda like this already - a much less integrated, but works via v4l2: https://developer.ridgerun.com/wiki/index.php/V4L2_FPGA https://developer.ridgerun.com/wiki/index.php/V4L2_FPGA
- johnea 3y agoI only know about xilinx specific, but even given the support for runtime updates to the FPGA logic that already exist in the xilinx kernels, there are serious roadblocks to updating only portions of the FPGA array. The logic must be very carefully implemented to allow over-writing only specific regions of the FPGA. If you're re-flashing the entire logic array, it's pretty straightforward. If you want to leave some logic in and add an additional funcitonality, this is much more difficult. This is really a limitaiton of the FPGA logic array implementation, not a linux shortcoming...
- jeffreygoesto 3y agoPartial reconfiguration is possible since twenty-something years but only a small percentage of problems really benefit from it, see i.e. https://www.fpgakey.com/tutorial/section742 https://www.fpgakey.com/tutorial/section742
- pantantrant 3y agoWhat percentage of problems would benefit from parallel reconfiguration? I'm raising money for an FPGA in my profile where programs aren't bottlenecked in FPGA reconfiguration but instead are reconfigured in parallel.
- jeffreygoesto 3y agoWithout really deep experience (my FPGA time ended 15ish years ago), I would say that granularity and frequency of the swapped out parts need to hit a sweet spot and you need to be able to hide that latency. If I understand you correctly, you tsrget the latter? But as with all pipelining you need do have an early trigger or lookahead.
- vitarnixofntrnt 3y ago[dead]
- deleted 3y ago[deleted]
- nxobject 3y agoThat would be very good for keeping devices useful far belong the lifetime of their hardware codecs, too - in a decade, when H.266 comes out, you’ll still be able to watch YouTube etc on your “vintage” computer.
- jauntywundrkind 3y agoIt'll be interesting to see if AMD can help unleash what Xilinx was. At some point, leaving FPGAs as cloistered inaccessible technology - even well supported cloistered technology - becomes a risk. Theres been some incremental improvement with low level Linux support across the past year. Good to seem but so far, actually using FPGAs is still all Vivado & closed systems. I think there's so much possibility left on the table by not supporting openfpga alternatives, not embracing yosys/openpnr/openroad/&al.
- buildbot 3y agoI hope AMD sees the light and helps F4FPGA develop a more complete open source toolchain for their FGPAs (https://f4pga.org https://f4pga.org). With this subsystem and an open source compilation flow, FGPA experiments would be way easier.
- UncleOxidant 3y agoUnfortunately this will never happen.
- hwbehrens 3y agoI don't know much about the ins-and-outs of the FPGA ecosystem -- can you explain why you think this kind of collaboration would be impossible? Is it a technical roadblock, a philosophical difference of opinion, a business decision, etc?
- PaulHoule 3y agoMy guess: if the bitstream format was documented competitors would know how the device works and be able to prove their patents are being violated. FPGA vendors will also justify inertia in that current FPGA users don’t seem to be deterred by the bad tools because of the economics of their business. Some think a lot of hobby users would try FPGA if the toolset was easier to pick up but there are not enough of those folks to keep Radio Shack or even Fry’s alive and they will be buying $5-$150 parts, not the much more powerful $10,000-$100,000 parts.
- JoshTriplett 3y ago> My guess: if the bitstream format was documented competitors would know how the device works and be able to prove their patents are being violated. This has been the persistent argument for many years from companies who say they can't release Open Source graphics drivers. > FPGA vendors will also justify inertia in that current FPGA users don’t seem to be deterred by the bad tools because of the economics of their business. Want hundreds as times as many FPGA users? Make it easy for an FPGA to be used for transparent acceleration, by making it easy for Open Source libraries to build and ship FPGA bitstreams that serve as accelerators for their data handling. Imagine if compression libraries, databases, and many other kinds of libraries could transparently take advantage of an FPGA if available to process data many times faster. Then there'd be a benefit to shipping an FPGA in many servers, and many client systems as well.
- johnea 3y agoDevicetree overlays and configfs has supported this in the xilinx kernels for some time. I guess what they're talking about is upstreaming all of this...
- monocasa 3y agoDo those existing kernel patches support dynamic devicetree overlays in a running system?
- mauchter 3y agoYes. See https://lore.kernel.org/all/1414528565-10907-1-git-send-email-pantelis.antoniou@konsulko.com/ https://lore.kernel.org/all/1414528565-10907-1-git-send-emai... (I believe the Xilinx-forked kernel uses a derivative of these patches)
- deleted 3y ago[deleted]
- synergy20 3y agohttps://www.kernel.org/doc/html/latest/driver-api/fpga/index.html https://www.kernel.org/doc/html/latest/driver-api/fpga/index... is the mentioned linux fpga framework, it would be very useful if a userspace API works.
- spacedcowboy 3y agoI wrote an internal proposal up for Apple to do this, about 17 years ago, while working on Aperture. Didn't get very far :(
- xattt 3y agoWas there any uptake when the Afterburner card came around?
- spacedcowboy 3y agoI mean Aperture was long gone when the Afterburner card came out. I was working in R&D by then…
- ApolIllo 3y agoI loved Aperture!
- vitarnixofntrnt 3y ago[dead]
- tuckerpo 3y agoOn-the-fly bitstream programming of FPGAs from a parallel Linux board used to mean holding the FPGA in reset and bit-banging the entire bitstream via the FPGA's passive or active serial interface, which is a blocking process that takes quite a bit of time. Be very nifty if this takes off.
- vitarnixofntrnt 3y ago[dead]
- aseipp 3y agoYeah, the existing FPGA device subsystem has been pretty much worthless for upstream kernels for years now and the lack of a good userspace API is a big reason, so in practice everyone just bitbangs the bitstream over some QSPI interface and pulls the reset manually. Hopefully this can see the light of day at some point.
- andrewstuart 3y agoWhat are the facts about how long AMD provides drivers for? Nvidia provide drivers for what feels like a VERY long time. I have the feeling that AMD gives up on providing drivers after only a few years of product life. But these are only hunches, anyone know the facts?
- bryanlarsen 3y agoStill on the front page: https://news.ycombinator.com/item?id=38868265 https://news.ycombinator.com/item?id=38868265
- andrewstuart 3y agoAre you sayig AMD provides drivers for 22 years just because that's a headline on HN? I don't believe that. My question stands - anyone have FACTS?
- bryanlarsen 3y agoI'm saying that you're posting your question on the wrong page. Your question is off topic here.
- andrewstuart 3y agoOH yes I see.
- madushan1000 3y agoAMD gpu drivers are in the linux kernel. They support even very old hardware. And linux only drops drivers when there are no users. So amd cards stay supported for basically their entire lifetime.
- falserum 3y agoMy current take is “program with if statements all the way down”->CPU, “Multiply these humongous matrix multiple times per second”->GPU. What is FPGA for?
- packetlost 3y agoIf you're thinking in terms of instructions or mathematics operations, you're thinking too high level for what an FPGA is and does. FPGAs are often times for prototyping hardware designs, but also for bespoke parallelized or hardware operations that are too low of yield to justify ASIC development.
- falserum 3y agoCPU -> is hardware meant to run any program. ASIC -> is hardware that may run only single program which is hardcoded into the chip. FPGA is something between CPU and ASIC. Right? (At eli5 level)
- vitarnixofntrnt 3y ago[dead]
- icf80 3y agocustom software in hardware, multiple times faster re-implement your own GPU?
- fayalalebrun 3y agoWith FPGA, unlike with GPUs, you can achieve significant speedup of algorithms where parallelization is very difficult. This is thanks to a technique called pipelining, where you can perform several steps of a sequential computation at the same time. An example of this is video decoding/encoding, which is commonly implemented by dedicated hardware.
- falcrist 3y agoAside from hardware prototyping, this seems to be the primary benefit of FPGAs. Much like if you assembled a system from glue logic, all of the operations in the pipeline and across the entire subsystem can happen simultaneously and often asynchronously with the only limitations being on clocked devices like flipflops and gated latches... and obviously whatever propagation delays the logic gates have (along with any protection from race conditions) Admittedly, I haven't had the opportunity to play with FPGAs very often in my professional career, but the limited experience I've had with them showed me you need an entirely different mindset when programming in a hardware description language. With assembly everything is global, and similarly with FPGAs almost everything is asynchronous and parallel.
- Lramseyer 3y ago> One of the major valid concerns that were raised with this configfs interface was security as it opens up the interface to users for modifying the live device tree. This has always felt like a gaping security hole waiting to be explored. Modern, high end FPGAs have a feature known as Raw SerDes, which in essence allows you to bypass a PCIe or Ethernet controller and use those lanes (yes, PCIe lanes) to your heart's desire ...provided you can design a working communication protocol. Difficult, but not impossible by any means. So if you wanted to, you could design your own PCIe controller and give it whatever device ID, vendor ID, memory space, or capability space you want! Normally these things are not writable on a PCIe controller. But if you designed your own, you could write them to whatever you want and spoof device types, memory spaces, or driver bindings, and probably get yourself access to memory you shouldn't be touching. While I don't know how the linux kernel would handle these potentially out of spec conditions, it never sat right with me from a security standpoint.
- mschuster91 3y ago> But if you designed your own, you could write them to whatever you want and spoof device types, memory spaces, or driver bindings, and probably get yourself access to memory you shouldn't be touching. Not in a system with a properly configured IOMMU unit. That stuff got some serious attention back in the old Thunderbolt 2 era, when people discovered that yes, it's PCIe under the hood and yes, having no IOMMU protection yields an attacker an instant-0wn.
- adwn 3y agoThe built-in Gigabit transceiver cores, which you'd have to use for the PCIe protocol, are connected to very specific IO pins on the FPGA. If the PCIe slots on your mainboard aren't already routed to those pins, then the FPGA will never be able to "bypass" the regular PCIe or Ethernet interfaces. Conversely, if they are connected to those pins, then the regular PCIe and Ethernet interfaces won't be able to use that PCIe slot. So no, your security concerns are unwarranted. > a feature known as Raw SerDes I have never heard anyone use the term "raw serdes" for hard transceiver IP cores.
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- Taniwha 3y agoAWS's FPGA instances (essentially a big xylinx on a PCIE board) are probably a good place to start here, any standard probably should allow for the multiple sorts of interfaces that those guys provide
- 15155 3y agoPCIE is too slow.
- jmrm 3y agoMore integration of FPGAs on computers can be really good to exploit relatively long pipeline algorithms that could run in parallel, specially signal processing ones. GPUs are really fast but using some kind of instructions, while on a FPGA you can practically design what "instruction" is going to run. From the limited experience I had on CUDA but the complexity of your algorithm and how much branches your code have can make your code a lot slower than running it on a CPU, no matter the amount of CUDA cores you have. It could be incredibly cool that in some near to mid future to being able to run an application that could run some kind of code in the FPGA, like they already does with the GPU, to solve some kind of problems, like audio, image, video processing, and probably machine learning (I don't know too much about current implementations), and with that user-space interface, it could even be earlier than I though.
- mips_r4300i 3y agoI'm all gung-ho for FPGAs since that's a huge part of my job, but I have to admit that GPUs will always be easier, faster, and more convenient for just about everything you'd want to do as some type of accelerator. There would only be exceptions for power usage, and maybe peak throughout. Where FPGAs shine best are in embedded or very obscure applications where GPUs are way too big, power hungry, or cannot support enough parallelization of your specific algo.
- teleforce 3y agoThis proposal together with CXL initiative I hope will seamlessly transform hardware-centric to software-centric computing world. We badly need them for the software-defined things (SD-X) namely software-defined radio (SDR), network (SDN), Instrumentation (SDI), etc, and Linux is at the forefront of the transformation.
- qrios 3y agoPossible fears about compromising the host system are of course justified. But such fears are appropriate for all DMA-capable devices, for example. FPGAs are general purpose in a broader sense than CPUs or (GP)GPUs. And, no other general purpose computing device is able to transport and compute incoming data in a pipeline in a few cycles (10, 100, whatever) from input to output. 30Gbyte per second? No problem. Under certain circumstances even guaranteed on a normal PC. A general interface such as a BIOS mapped into the memory would be interesting for many applications. Apple has taken a good step with the Afterburner (like others before it in the music and movie sector). After the coin hype, FPGAs once again disappeared into the niche of high-frequency trading, only to become popular in the low-price spectrum of chips for console emulators in recent years. No cloud provider has managed to bring FPGAs to the masses. Intel and AMD have bought the market leaders and have blown all efforts to achieve something in the data centers. AMD seems to take the first step: introduction of a general interface. The directly necessary next step would be something like CUDA (apart from IP, the name once stood for "Compute Unified Device Architecture") instead of VHDL or Verilog. It doesn't even have to be open source. It has to be something where you can compile a demo program (Mandelbrot and RISC V and 68030) in five minutes and get it running (and don't always tell everyone that it's called "synthesizing"). On a PC with a typical graphics card, place & route would be much faster. But not with a tcl/tk interface in Java as with Vivado.