4 ms·

https://www.princeton.edu/~minjie/files/jaeil_apec20_paper.pdf https://www.princeton.edu/~minjie/files/jaeil_apec20_paper.p... People are waaaay ahead of you. T

• crote 3y ago
  Note that the paper you linked is still doing a two-step conversion - they essentially just removed the capacitors between the two steps. It doesn't do 48V -> 1.5V, it does 48V -> 8V -> 1.5V. They even specifically point out the downsides of single-stage conversion topologies.
• xxs 3y ago
  "It leverages the high performance of low voltage DrMOS devices and multiphase buck control", drmos is driver and mosfet. Like mentioned (by a sibling comment), it's not a single conversion, but the efficiency is not the prime issue regardless - it's the reaction time and the voltage sag. Load insertion causes the voltage at the CPU (inside) to drop and be significantly lower than the one measure at at the VRM, due to losses at such high currents. The lack of voltage simply causes the systems to crash.