2 ms·

Is it possible to use big and fat CPU registers instead of cache? There might be no wasted clock cycles and no delay.

Dylan16807 3y ago
Registers are quite expensive in space and power, because multiple at once have to be accessible in many places. If you add more registers, the cost per register increases rapidly, and you very quickly hit your limits. If you make registers wider, that's still very expensive, and you introduce extra steps to get to your data most of the time. So no, you can't do that in a reasonable way.
- DeathArrow 3y ago
  Thank you!
Nevermark 3y ago
A compiler AND processor design amateur here. (Latter in school.) Once you have enough registers, having more mean lowers active utilization for any given instruction (bad use of space, vs. fast pipelined access to cached stack) or higher levels of parallel instruction dispatch (much greater complexity, and even greater inefficiency for branching misses). Then you have to update instruction sets, which could be impossible given how tightly they fit in current instruction sizes. Ergo, increasing register banks is a major architecture & platform change from hardware to software redesign, with heavy end user impact, and a fair chance of decreasing performance. In contrast, anything that improves caching performance is a big non-disruptive win.
- als0 3y ago
  What about if you use register windows or special renaming of architectural registers to internal ones? https://en.wikipedia.org/wiki/Register_window https://en.wikipedia.org/wiki/Register_window
  - Nevermark 3y ago
    The amount of stack in the L1 cache is essentially that. A shifting fast access working memory area. Then think of registers as just part of the fetch & store pipelines for staging operations on stack values. Forth goes all in with this approach.
saati 3y ago
CPU registers are either SRAM or even larger flip-flops, they have the same problem.

Registers are quite expensive in space and power, because multiple at once have to be accessible in many places. If you add more registers, the cost per register increases rapidly, and you very quickly hit your limits. If you make registers wider, that's still very expensive, and you introduce extra steps to get to your data most of the time. So no, you can't do that in a reasonable way.

DeathArrow 3y ago
Thank you!

Nevermark 3y ago

A compiler AND processor design amateur here. (Latter in school.) Once you have enough registers, having more mean lowers active utilization for any given instruction (bad use of space, vs. fast pipelined access to cached stack) or higher levels of parallel instruction dispatch (much greater complexity, and even greater inefficiency for branching misses). Then you have to update instruction sets, which could be impossible given how tightly they fit in current instruction sizes. Ergo, increasing register banks is a major architecture & platform change from hardware to software redesign, with heavy end user impact, and a fair chance of decreasing performance. In contrast, anything that improves caching performance is a big non-disruptive win.

als0 3y ago
What about if you use register windows or special renaming of architectural registers to internal ones? https://en.wikipedia.org/wiki/Register_window https://en.wikipedia.org/wiki/Register_window
- Nevermark 3y ago
  The amount of stack in the L1 cache is essentially that. A shifting fast access working memory area. Then think of registers as just part of the fetch & store pipelines for staging operations on stack values. Forth goes all in with this approach.

saati 3y ago

CPU registers are either SRAM or even larger flip-flops, they have the same problem.