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General question about semiconductors: Why is there so much emphasis on the density of transistors rather than purely on the costs of production (compute/$)? CP
by bogtog 3y ago
General question about semiconductors: Why is there so much emphasis on the density of transistors rather than purely on the costs of production (compute/$)? CPUs aren't particularly large. My computer's CPU may be just a few tablespoons in volume. Hence, is compute less useful if it's spread out (e.g., due to communication speeds)?
- nsonha 3y agothe physical limitation of more CPUs: heat, which in turn downgrades performance
- mikepurvis 3y agoBut I think the GP's point is that heat is far easier managed when spread out over a larger area, so why all the emphasis on ultra tiny transistors vs just making a chip that's two inches by two inches or something? And I think the main answer to that comes when you look at some of the discourse around Apple's M-series chips, that doing a larger-die design is just way riskier: there are huge implications on cost, yield, flexibility, etc, so it was really something that Apple was uniquely positioned to move aggressively on vs a player like Qualcomm who needs to be way more conservative in what they try to sell to their main customers (phone OEMs like Samsung).
- dist-epoch 3y ago> making a chip that's two inches by two inches These already exist. Lookup images of AMD Ryzen Threadripper PRO 7995WX - 96 cores: https://www.techpowerup.com/img/fp51OPD4JRS7wvTK.jpg https://www.techpowerup.com/img/fp51OPD4JRS7wvTK.jpg
- dontlaugh 3y agoThose are made up of much smaller chiplets. No individual die is all that big
- ls612 3y agoOh the reason they don’t make dies that big is the probably of a defect balloons and your yields would be shit.
- mikepurvis 3y agoApple handles that in part by fusing off the broken subcomponents of the huge die, though, which is how they end up with stuff like a 7-core GPU.
- Detrytus 3y agoEvery chip manufacturer does that, that's how they come up with cheap, low end parts. They just try to keep number of cores an even number, so the trick is less obvious.
- twobitshifter 3y agoI believe this was some of the advantage of the AMD Zen series of chips which moved to a larger die size from Athlon.
- wahnfrieden 3y agoYes, electricity doesn’t move instantly
- xhrpost 3y agoYou could always purchase a multi CPU system (effectively what you're suggesting) from several years ago for much cheaper than modern hardware. If you're using it regularly though, the electrical cost will eventually eat away any money savings vs the same computational power in a modern single CPU.
- xbmcuser 3y agoWith the way Solar/wind + batteries are bringing electricity prices down the cost per compute will still come down even as moore laws slows down. Looking at current trends running today processors 10 years from now could just cost in electricity just 10-12% what it costs now.
- foolfoolz 3y agoreducing costs is nice for consumer… making cpu higher cost that goes brrrrt is better for business
- sabbey 3y agoLight travels at one foot per nanosecond. So a processor one foot wide you'd expect to run at 1 GHz max.
- _8j50 3y agoOnly if it is so badly designed that data needs to cross the entire dye's cross section.
- cma 3y agoLook at how much space cache uses on a die.
- _8j50 3y agoThe core would use cache near it? Memory access delay such as caches is not considered part of cpu frequency either afaik.
- tux3 3y agoCache takes X number of cycles to return a result You can make X lower by reducing the frequency (= having each cycle be longer) But apart for that, the main reason big chips would clock slower is power, not timing. If you have a lot of transistors all switching on a high voltage so that the frequency is high, you get molten metal and the magic smoke leaves. Big chips aren't one big stage where light travels from one side to the other. But they are giant weaves of heating elements that can't all run fast all of the time
- markhahn 3y agocache latency is definitely part of what limits core clock. you're not going to have a good time if your L1 latency is, say 10 clocks. not to mention the fact that register files are not much different than SRAM (therefore cache-like).
- _8j50 3y ago
- uluyol 3y agoDensity is one of the main ways to get cost savings. But there are others too, and there's also a lot of hype around them. Chiplets for example. Or CXL for memory.
- Salgat 3y agoPersonal usage still relies on fast single threaded performance. As far as business usage, the cost is primarily energy which requires smaller node size for the same performance.
- noam_k 3y agoIn addition to the answers already given, there are defects during the process that are more likely to render your chip useless the larger your chip is. This is true for smaller chips as well, and often the design handles a defunct component, but you prefer minimizing defects per chip.
- DeathArrow 3y agoWhat do you mean by spread? Multi socketed mainboards? That would help only for parallelizable workloads. For many workloads is the single threaded performance that matters most.
- brennanpeterson 3y agoIt is? A factory makes transistors ,and if you increase a 'node', you make twice as much. If you do an amazing job, you might reduce cost 10%. So by far the best way to maximize value in semiconductors is to enable shrink. But you also just don't hear it in the popular or even engineering press. Most manufacturers and designers look at a PPAC curve (power, performance, area, cost) and find optimal design points. As for spreading it out: the unit of production isn't a wafer, it is a lithographic field, which is roughly 25*35mm. You cant practically 'speead out' much more (ok, you sort of can with field stitching, but that is really expensive).
- iopq 3y agoBecause when you make it denser, you can cut the CPU into smaller parts, which decreases costs when you make it less dense, it can clock up higher, but you will have fewer cores per mm^2 AMD went with both approaches, where their hybrid CPU will have densely packed low speed Zen 4C cores and some high speed Zen 4 cores to boost at the highest frequency
- cubefox 3y agoIncreasing density has caused chip cost per FLOP/s to decrease exponentially over the last decades. But nowadays the price per transistor doesn't go down as fast with increased density like it used to. E.g. new Nvidia GPUs are getting smaller for the same price, which means they are getting more expensive for the same size. At some point, the price per transistor will actually increase. Then Moore's Law (the exponential increase in transistor density) will probably stop, simply because it's not economical to produce slower chips for the same price. (Maybe the increased power efficiency will still make density scaling worth it for a little while longer, but probably not a lot longer.)
- jpgvm 3y agoThis isn't due to fundamental cost increasing per transistor though, this is because NVidia changed their pricing strategy to decouple it from that. They are simply making greater % profit/transitor.
- FirmwareBurner 3y ago> this is because NVidia changed their pricing strategy to decouple it from that Because neither AMD nor Intel can come withing striking distance of Nvidia's flagships, and seeing how their silicone flies off the shelves, they have also adjusted their pricing to match their relative performance to Nvidia.
- iopq 3y agoYou're talking about one product, which is the 4090, which is 0.88% of all GPUs used by Steam users [0] The top GPU is the 3060, at 4.89% which both Intel and AMD match with their offerings [1] The top AMD dGPU is still the RX 580 at 0.97% [0] https://store.steampowered.com/hwsurvey/Steam-Hardware-Software-Survey-Welcome-to-Steam https://store.steampowered.com/hwsurvey/Steam-Hardware-Softw... [1] https://youtu.be/aXU9wee0tec?t=834 https://youtu.be/aXU9wee0tec?t=834
- imtringued 3y agoBecause you are assuming there is an objectively optimal processor design for a specific manufacturing process. If you don't constrain the chip to a specific design then what is going to count as compute? The number of adders or multipliers? That is just a different way of talking about transistor density.
- markhahn 3y agocost is area, because defects. TOF latency isn't that much of a big deal, though driving a signal for distance consumes a lot of power, and power has been the primary design-limiter for at least a decade.