Verilog isn't slow to compile to RTL. The problem is after it's compiled and 'linked', laying out and routing it efficiently on the fpga takes a lot of compute

Verilog isn't slow to compile to RTL. The problem is after it's compiled and 'linked', laying out and routing it efficiently on the fpga takes a lot of compute as the occupancy and timing requested gets closer to the edge of what's possible on the device. On the plus side, you can quickly iteratively compile and simulate your change to confirm it is logically correct before putting it on the fpga.