3 ms·

It doesn't work like that, the 40gbps is actual bus bandwidth AFAIK. https://www.thunderbolttechnology.net/sites/default/files/Thunderbolt3_TechBrief_FINAL.pdf

by chx 3y ago

It doesn't work like that, the 40gbps is actual bus bandwidth AFAIK. https://www.thunderbolttechnology.net/sites/default/files/Thunderbolt3_TechBrief_FINAL.pdf https://www.thunderbolttechnology.net/sites/default/files/Th... figure 7 says 5120 x 2880 @ 60Hz which requires 22.18gbit/s leaves 18gbps data bandwidth. (This figure is quite important because this is one of the two only "official" sources which admits the raw data transfer limit of TB3 is 22gbps, the other is Dell at https://www.dell.com/support/kbdoc/en-uk/000149848/thunderbolt-3-usb-c-maximum-data-transfer-rate-on-dell-systems https://www.dell.com/support/kbdoc/en-uk/000149848/thunderbo... otherwise you'll only see the 40gbps speed.) What happens rather is much simpler, the blog post forgot to set the calculator to 10 bit https://linustechtips.com/topic/729232-guide-to-display-cables-adapters-v2/?section=calc&H=6016&V=3384&F=60&bpc=10&calculations=show&formulas=show https://linustechtips.com/topic/729232-guide-to-display-cabl... if they did you'd see the data rate required is 38.20gbit/s so the bus is near full. USB C has separate 2.0 wires so unless you have DP 1.4 for DSC you can only use those for USB data, there's no space for anything else.

korhojoa 3y ago
That's not really the full story, when this is about displays. I currently have a display that requires Displayport 2.1 to get everything out of it, and with DSC and DP 1.4, I can get a "theoretical bitrate" that is higher than what they would normally allow. (Of course, this doesn't change what the link can do, it just allows you to do more with the same bandwidth) On thunderbolt 3 systems, the link is on HBR3, which with DSC allows 120hz, 10bit at 7680x2160. No DSC support limits the refresh to 60hz and 8bit (as then you won't have the higher rates available anyway, since DSC is mandatory with newer standards). You can check https://tomverbeure.github.io/video_timings_calculator https://tomverbeure.github.io/video_timings_calculator to see what is possible.
brigade 3y ago
Thunderbolt 3 doesn't use those USB 2.0 wires; that was one of the big changes in USB4/TB4 to use them. Once you're in Thunderbolt 3 mode, all USB ports are provided by PCIe xHCI controllers by the TB3 device. In actuality, the mode where the XDR display consumes 38gbps of uncompressed display bandwidth is an Apple-only mode requiring special Titan Ridge firmware that aggregates 6 lanes of HBR3. Contrary to the article, Alpine Ridge does not support 6k, which specifically is why the iMac Pro doesn't support 6k output. It requiring special firmware is also why this mode only works when directly connected to the Mac. But yeah, it's annoying that everyone throws bandwidth numbers around without mentioning or even thinking if it's link rate or data rate.
- deleted 3y ago
  [deleted]
- dataworm 3y ago
  I'm not sure about this mode requiring special Apple firmware, but it definitely does not use 6 lanes of HBR3: https://forums.macrumors.com/threads/caldigit-introduces-usb-c-dock-with-10-ports-and-up-to-94w-charging-for-macs-updated.2280085/page-4?post=29502187#post-29502187:~:text=for%20the%20host.-,No%20such%20thing%20as%206%20lanes%20of%20HBR3.%20A%20DisplayPort%20connection%20uses%201%2C%202%2C%20or%204%20lanes.%20The%20XDR%20uses%20two%20DisplayPort%201.4%20connections%20of%204%20lanes%20each.,-The%20AGDCDiagnose%20output7 https://forums.macrumors.com/threads/caldigit-introduces-usb.... I don't think Thunderbolt ever uses anything other than 4 lanes per DP connection if the GPU doesn't limit the lane count, because Thunderbolt deserializes DP packets, transmits them over the link and serializes them back on the other end, so it can't negotiate the lane count on the host side.
- chx 3y ago
  Thunderbolt 3 uses the four high speed lanes of the USB C connector. The USB 2.0 separate wires are present and are definitely used. Yes, it's USB4 which added USB packets to the bus, TB3 only had PCIe and DP. That's rather interesting there, what do you mean by aggregating? Thunderbolt could always carry 40gbps worth of DisplayPort packets and afaik it was not lane bound.
  - brigade 3y ago
    I mean, if you have access to the actual Thunderbolt spec saying otherwise then so be it. Personally, I sincerely doubt that the PCIe packets containing USB 2.0 data are specially routed over the USB 2.0 wires like you say since that runs counter to literally everything public about how Thunderbolt 3 works. Maybe the spec itself doesn't define a maximum bandwidth allocation for DisplayPort packets, but the DisplayPort stream has to come from somewhere and be output somewhere else, and with one single exception, the actual implementations support two HBR2 streams or one HBR3 stream, with each stream obviously being individually capped to 4 lanes at the physical DP interface. (AFAIK the special mode combines one 4-lane HBR3 stream with a second 2-lane HBR3 stream)

by chx 3y ago

korhojoa 3y ago

That's not really the full story, when this is about displays. I currently have a display that requires Displayport 2.1 to get everything out of it, and with DSC and DP 1.4, I can get a "theoretical bitrate" that is higher than what they would normally allow. (Of course, this doesn't change what the link can do, it just allows you to do more with the same bandwidth) On thunderbolt 3 systems, the link is on HBR3, which with DSC allows 120hz, 10bit at 7680x2160. No DSC support limits the refresh to 60hz and 8bit (as then you won't have the higher rates available anyway, since DSC is mandatory with newer standards). You can check https://tomverbeure.github.io/video_timings_calculator https://tomverbeure.github.io/video_timings_calculator to see what is possible.

brigade 3y ago

Thunderbolt 3 doesn't use those USB 2.0 wires; that was one of the big changes in USB4/TB4 to use them. Once you're in Thunderbolt 3 mode, all USB ports are provided by PCIe xHCI controllers by the TB3 device. In actuality, the mode where the XDR display consumes 38gbps of uncompressed display bandwidth is an Apple-only mode requiring special Titan Ridge firmware that aggregates 6 lanes of HBR3. Contrary to the article, Alpine Ridge does not support 6k, which specifically is why the iMac Pro doesn't support 6k output. It requiring special firmware is also why this mode only works when directly connected to the Mac. But yeah, it's annoying that everyone throws bandwidth numbers around without mentioning or even thinking if it's link rate or data rate.

deleted 3y ago
[deleted]
dataworm 3y ago
I'm not sure about this mode requiring special Apple firmware, but it definitely does not use 6 lanes of HBR3: https://forums.macrumors.com/threads/caldigit-introduces-usb-c-dock-with-10-ports-and-up-to-94w-charging-for-macs-updated.2280085/page-4?post=29502187#post-29502187:~:text=for%20the%20host.-,No%20such%20thing%20as%206%20lanes%20of%20HBR3.%20A%20DisplayPort%20connection%20uses%201%2C%202%2C%20or%204%20lanes.%20The%20XDR%20uses%20two%20DisplayPort%201.4%20connections%20of%204%20lanes%20each.,-The%20AGDCDiagnose%20output7 https://forums.macrumors.com/threads/caldigit-introduces-usb.... I don't think Thunderbolt ever uses anything other than 4 lanes per DP connection if the GPU doesn't limit the lane count, because Thunderbolt deserializes DP packets, transmits them over the link and serializes them back on the other end, so it can't negotiate the lane count on the host side.
chx 3y ago
Thunderbolt 3 uses the four high speed lanes of the USB C connector. The USB 2.0 separate wires are present and are definitely used. Yes, it's USB4 which added USB packets to the bus, TB3 only had PCIe and DP. That's rather interesting there, what do you mean by aggregating? Thunderbolt could always carry 40gbps worth of DisplayPort packets and afaik it was not lane bound.
- brigade 3y ago
  I mean, if you have access to the actual Thunderbolt spec saying otherwise then so be it. Personally, I sincerely doubt that the PCIe packets containing USB 2.0 data are specially routed over the USB 2.0 wires like you say since that runs counter to literally everything public about how Thunderbolt 3 works. Maybe the spec itself doesn't define a maximum bandwidth allocation for DisplayPort packets, but the DisplayPort stream has to come from somewhere and be output somewhere else, and with one single exception, the actual implementations support two HBR2 streams or one HBR3 stream, with each stream obviously being individually capped to 4 lanes at the physical DP interface. (AFAIK the special mode combines one 4-lane HBR3 stream with a second 2-lane HBR3 stream)