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I’m all for new soft cores. However, do we really need to pollute the name space? Microblaze is already a name of an architecture that somebody might want to Go
by dmitrygr 3y ago
I’m all for new soft cores. However, do we really need to pollute the name space? Microblaze is already a name of an architecture that somebody might want to Google.
Just call it AMDcoreV or some such thing
- ynx 3y ago...as in the MicroBlaze architecture owned by AMD by way of its acquisition of Xilinx?
- tw04 3y agoCorrect, microblaze is the name of an architecture AMD owns, and this is compatible with, per the article. > It allows developers to leverage the open-source RISC-V software ecosystem, is hardware compatible with the classic MicroBlaze processor
- mkj 3y agoWhat does "hardware compatible" mean here though? It runs on the same FPGA hardware, but has unrelated CPU architecture?
- namibj 3y agoI assume it means it's essentially pin-compatible, like, say, a PCIe GPU upgrade would be. Still needs new software. But has the same HDMI and PCIe and the same low-level protocols.
- AlotOfReading 3y agoSoft cores don't have their own pins. I think "hardware compatible" means that it runs on the same FPGAs as microblaze arm with the same toolchain product suite.
- addaon 3y ago"Pins", in this case, means the logical ports used to interface one module within an FPGA to another. Think AMBA bus, clock(s), interrupt lines, etc. An FPGA SOC design that currently throws a bunch of different IPs (modules) together to do... something... could do the same with this core thrown in to replace a (classic) Microblaze with only a resynthesis on the hardware side, and a recompile on the software side.
- brucehoult 3y agoIt has the same interface to the rest of the design -- the buses and control signals etc. You can drop the new RISC-V soft core straight into an existing design using Microblaze and change only the program code.
- sassy_quat 3y ago[dead]
- hajile 3y agoCPU is just one part. You're probably adding your own coprocessor and whatever other IO to the FPGA. If the CPU uses a different interconnect/protocol design, you'll have to redesign and debug your entire interface which will be very expensive. Meanwhile, microblaze is a proprietary architecture. AMD puts a few hundred thousand dollars of dev time into it here or there, but most software stacks will have tons of stuff not at all designed for that ISA. If you can switch to RISC-V, you get access to an ecosystem where tons of companies are all pouring multi-millions in every year. EDIT: a great example is that microBlaze was added to LLVM in 2010, but then removed in 2013 because nobody was free to maintain it. Now AMD comes along and says you can swap out the CPU ISA to RISC-V without needing any hardware redesigns and then with a simple recompile, you can start using that massive ecosystem instead of spending man-years writing your own stuff which saves your company lots of money.
- FastFT 3y agoHardware compatible doesn’t mean very much in this case. It’s a different ISA so you’ll need a different tool chain and recompilation (possibly rewrite given that assembly is very common in deeply embedded processors). It’ll also have different LUT usage, etc.
- tails4e 3y agoIt means it's designed as a direct drop in replacent for a traditional microblaze ISA code..sure software must be recompiled, but hardware interfaces match what was there before for peripheral access, debug, instruction offload, etc. This makes the transition to using RISC-v much more seamless if you were already using microblaze
- pclmulqdq 3y agoThis is the new Xilinx Microblaze. They went from an AVR-like instruction set to RV32.
- 8K832d7tNmiQ 3y agoor simplify it as AMD V core to make it easier to say.
- userbinator 3y agoNot to be confused with AMD-V, the existing virtualisation extension (subtly different from and incompatible with Intel's VT-x) for its x86 CPUs.
- snvzz 3y ago"AMD V core" would only work (ignoring AMD-V virtualization assisting x86 extension) if AMD only ever planned to make one RISC-V core. I am looking forward to Zen-V.
- snvzz 3y agoIt is the same interface facing your HDL. Whereas on the software side, it is RISC-V, the ISA that's rapidly growing the strongest ecosystem. Just a recompile away, except this time, you don't have to deal with poor, proprietary, bespoke, low quality tooling, but you can instead use reputable industry standard tools like gcc, binutils, llvm.
- opello 3y agoI'm pretty sure the "bespoke" tooling was just older versions of those industry standard tools because of poor upstreaming of architecture support. And there are probably many, very reasonable, justifications for that having been the case... the least of which is shipping toolchains with their own design tools. RISC-V doesn't seem like the "strongest" ISA ecosystem, unless you mean among soft core CPUs?
- fleventynine 3y agoAmong 32-bit microcontroller-class architectures, modern toolchain support for rv32imc is second only to armv7m IMHO. Nobody wants to maintain support for any other vendor-specific ISAs.
- brucehoult 3y agoStrongest of any ISA after ARM and x86 at this stage, I should think. I can't really see AMD/Xilinx or Intel/Altera offering a free 486SX soft core, even though they legally could. It would I expect use a lot more LUTs, and be slower. Licensing Cortex-M1 doesn't seem likely either.
- jaeckel 3y agoBeides that there are ARM softcores available on Xilinx... https://www.arm.com/resources/free-arm-cortex-m-on-fpga https://www.arm.com/resources/free-arm-cortex-m-on-fpga
- snvzz 3y ago>unless you mean among soft core CPUs Note that RISC-V hard cores in FPGAs are already a reality, including Microsemi PolarFire as well as GOWIN GW2N. Not long from now, I expect every FPGA vendor to switch over. The ones that already offer soft cores won't take long. >RISC-V doesn't seem like the "strongest" ISA ecosystem RISC-V is rapidly building the strongest ecosystem. It already is the strongest besides x86 and ARM, and the position of these two isn't, by any means, secure.
- opello 3y agoAt least it's "MicroBlaze V" which is better than no affix.