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Ask HN: Apple launches M3 with 3nm tech,how far are we from end of Moore's Law?
Apple today introduced M3 range of laptops which uses 3-nm technology [1]
Moore's law has been driven primarily by the reduction in transistor sizes. How far does this go?
Can we go to sub-1nm or is there a limit here and then Moore's law ends? AFAIK at smaller sizes quantum tunneling starts coming into picture. What happens when we hit that limit?
[1]https://www.apple.com/macbook-pro/
- gloyoyo 3y agoSub-nano all the way!
- schoen 3y agoA frustrating thing is that the process node name has decoupled from the feature size: > Later each new generation process became known as a technology node or process node, designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994, and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per square millimeter). So each recent process has an explanation on Wikipedia like > The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers. Respectively from https://en.wikipedia.org/wiki/Semiconductor_device_fabrication#Process_size https://en.wikipedia.org/wiki/Semiconductor_device_fabricati... https://en.wikipedia.org/wiki/3_nm_process https://en.wikipedia.org/wiki/3_nm_process
- pranay01 3y agoSo, is 3nm not thinner/smaller in size compared to 5nm?
- reroute22 3y agoI think there is a bit of an exaggeration in the previous comment. Feature sizes decoupled from process node names mid-90s somewhat mildly, with transistor density remaining accurate to the naming. With introduction of FinFET transistors (2012, Intel 22nm), feature size and node naming truly decoupled completely, but node naming still remained largely true to transistor density. Transistor density started drifting apart from the node naming only recently, and in part it has to do with ever increasing difference in transistor density and its rate of improvement in different parts of the design, especially between logic (shrinks the fastest), SRAM (used for various caches and even register files), and IO (like DRAM controllers, shrinks the slowest). 3nm is smaller than 5nm. It's just there is quite literally not a single meaningful distance measurement in a 3nm design that measures 3nm, just like there is nothing 5nm in a 5nm design - most features are much larger than that physically. Further, (5/3)^2 ~= 2.8 may suggest that this is a 2.8x increase in transistor density, which it absolutely isn't, it's just nobody wanted to name the node 3.5 to yield more accurate and very traditional 2x ratio ((5/3.5)^2 ~= 2). Furthermore, even 2x would be misleading, only logic density increase somewhat approaches that figure: logic: 1.7x SRAM: 1.25x IO: 1.11x As chips contain all of these components, overall external area (physical size of the entire finished chip) of real-world chips going from 5nm to 3nm is shrinking by about 1.3-1.4x or so, far cry from (very) old school 2x, never mind 2.8x that naming may suggest. To make things even more complicated, the following is also true: long time ago the cost of the chip was practically proportional to its area almost regardless of the process node used, therefore, 2x smaller chip costed almost 2x less to produce. Not anymore. Now every new node is substantially more expensive per unit area to use, thus a smaller chip on a newer node ends up costing only marginally less - and in some instances, more - than a bigger (by area) chip on an older node.
- KingLancelot 3y ago[dead]
- KingLancelot 3y ago[dead]
- ilaksh 3y agoThere's a lot more to optimizing comouting than just the size and number of transistors. Such as branch prediction and many other aspects. Also, gaming and ML training rely on massive parallelism. So that's another paradigm. More new paradigms like memory-centric and/or analog computing for AI will be commercialized in the next several years.
- rl1987 3y agoI thought Moore's law ended years ago and the current transistor sizes are merely marketing numbers?
- pranay01 3y agoI see, can you explain. Aren't transistor sizes still reducing which is what Moore's law predicted (being able to fit more transistors in a wafer)?
- mattbrewsbytes 3y agoI believe the reason the industry went with multi-core chips is because they hit a wall (so to speak) with the actual transistor counts per chip. I would wager a guess that most people have CPUs that are over-powered for their needs. I'm not saying researching and improvement is a waste of time, just that for 95% of the people, buying bleeding edge computers is a waste of money.
- coolvision 3y agoMoore's law is not about transistor sizes, it's for number of transistors on a chip. This is still going strong, at least for the next few years.
- thiago_fm 3y agoShort answer: it isn't, this 3-nm is a marketing term, they keep redefining the term to use a lower and lower number. Transistor body dimensions is at or below about 7nm start having some quantum effects. Here's a reddit post where there's more detail about the physics and science behind this: https://www.reddit.com/r/askscience/comments/itiuw8/how_are_chip_manufacturers_getting_around_quantum/ https://www.reddit.com/r/askscience/comments/itiuw8/how_are_...