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Are there simulators that chip developers use to get an idea of what performance will be for certain workloads prior to creating an engineering sample? Or how

Are there simulators that chip developers use to get an idea of what performance will be for certain workloads prior to creating an engineering sample? Or how does this work?

frogblast 3y ago
Ideally they know exactly how it will perform: Every part of the chip, including the caches, memory controller, and DRAM is implemented in a cycle accurate simulator. There are often multiple versions of that simulator, one written in C/C++ that matches the overall structure of the eventual hardware, and then simulations of the actual RTL (hardware source code, networks of gates). The C-model and RTL model outputs are often also compared with each other as a correctness validation step, as they should ideally never diverge. (ie, implement twice, by two teams, and cross-check the results). Those simulations are terrifically slow for larger chips, so there is a surprisingly small number of workloads that can be run through them in reasonable time. So there tend to be even more simulator implementations that sacrifice perfect performance emulation for 'good enough' performance correlation (when surprises can happen). Being able to come up with a non-exact simulator that perf-correlates with real hardware is an art in itself.
- sol91949 3y ago
  Are the C simulators hand crafted each time by the chip designer? It seems like the kind of thing that needs custom built but I’m wondering if there is a common toolset used, or platform?
  - wmf 3y ago
    For production chips the simulators are usually completely custom. In academia people tend to modify existing simulators like SimpleScalar or Gem5.
    - sol91949 3y ago
      Many thanks for the insight
- KptMarchewa 3y ago
  The "exact" part is not exactly true for modern computer processors, where thermal and power constraints are a problem, right?
  - wmf 3y ago
    The performance team usually thinks in terms of cycles. At runtime the frequency varies depending on various factors as you said, but this is mostly ignored.
universal_sinc 3y ago
Absolutely! Chip designers have a several tools to do this. First, they create detailed software models (usually in C++) of their chips to estimate performance as closely as they can before laying out a single transitory. These models can run code just like a real hardware device, albeit slowly. Once the chip is designed, verilog simulators are programs used to generate the exact logical output of a circuit, which can be used to measure performance on a workload. However, this method is even slower than the first! For larger workloads and higher speed, they use extraordinarily expensive FPGA-based platforms called Emulators. This allows circuits to be run at speeds in the MHz range before ever being sent to a fab. Booting an OS, running a complex multicore workload with shared memory, they can measure almost any workload. But this method is not available until late in the design phase and the boxes themselves are prohibitively expensive from being deployed very widely. The software models are the most useful for estimating performance, as long as they are written early and well :)
- vintagedave 3y ago
  > they create detailed software models (usually in C++) of their chips to estimate performance as closely as they can How does this work? Do they model at the transistor level, or at the level of logical functions, or..? I'm particularly curious how this can estimate performance if it's anything higher-level than a direct transistor-for-transistor, layout-aware, emulation. I'd be really interested in learning more if there's anything you could share, please. I can find info about chip design software and languages like Verilog (as you mention) but not this sort of modeling.
  - nudgeee 3y ago
    When I was in chip design about 15 years ago, we did transaction level modeling (TLM) using SystemC. Not sure if it’s still a thing these days. https://en.m.wikipedia.org/wiki/Transaction-level_modeling https://en.m.wikipedia.org/wiki/Transaction-level_modeling
  - amelius 3y ago
    Basically you model all the elements of a chip (queues, memory, alus, etc), and how much time they take. You use a virtual clock so your simulation model can run at a different pace.
synergy20 3y ago
systemc is a c++ derivative often used to model chip designs. Before chip tapeout most of the chip design has been fully simulated and emulated many many times, be it functional wise, or cycle by cycle(e.g. cycle accurate simulation).
- andromeduck 3y ago
  That just gave me PTSD. System C is terrible.
  - synergy20 3y ago
    it's c++17 for me, I don't feel much difference at all between c++ and systemc.
epilys 3y ago
Arm has "Fast Models": https://developer.arm.com/Tools%20and%20Software/Fast%20Models https://developer.arm.com/Tools%20and%20Software/Fast%20Mode...
- StillBored 3y ago
  Those aren't for quantifying performance, they are for developing the firmware/OS/software stack to run on the platform. In other words, they are a slightly more accurate version of something like QEMU, although I guess I should point out they can generate traces that can be fed into tools to model HW perf, ex gem5.
  - epilys 3y ago
    Second sentence in link: "They allow full control over the simulation, including profiling, debug and trace."

Are there simulators that chip developers use to get an idea of what performance will be for certain workloads prior to creating an engineering sample? Or how does this work?

frogblast 3y ago

Ideally they know exactly how it will perform: Every part of the chip, including the caches, memory controller, and DRAM is implemented in a cycle accurate simulator. There are often multiple versions of that simulator, one written in C/C++ that matches the overall structure of the eventual hardware, and then simulations of the actual RTL (hardware source code, networks of gates). The C-model and RTL model outputs are often also compared with each other as a correctness validation step, as they should ideally never diverge. (ie, implement twice, by two teams, and cross-check the results). Those simulations are terrifically slow for larger chips, so there is a surprisingly small number of workloads that can be run through them in reasonable time. So there tend to be even more simulator implementations that sacrifice perfect performance emulation for 'good enough' performance correlation (when surprises can happen). Being able to come up with a non-exact simulator that perf-correlates with real hardware is an art in itself.

sol91949 3y ago
Are the C simulators hand crafted each time by the chip designer? It seems like the kind of thing that needs custom built but I’m wondering if there is a common toolset used, or platform?
- wmf 3y ago
  For production chips the simulators are usually completely custom. In academia people tend to modify existing simulators like SimpleScalar or Gem5.
  - sol91949 3y ago
    Many thanks for the insight
KptMarchewa 3y ago
The "exact" part is not exactly true for modern computer processors, where thermal and power constraints are a problem, right?
- wmf 3y ago
  The performance team usually thinks in terms of cycles. At runtime the frequency varies depending on various factors as you said, but this is mostly ignored.

universal_sinc 3y ago

Absolutely! Chip designers have a several tools to do this. First, they create detailed software models (usually in C++) of their chips to estimate performance as closely as they can before laying out a single transitory. These models can run code just like a real hardware device, albeit slowly. Once the chip is designed, verilog simulators are programs used to generate the exact logical output of a circuit, which can be used to measure performance on a workload. However, this method is even slower than the first! For larger workloads and higher speed, they use extraordinarily expensive FPGA-based platforms called Emulators. This allows circuits to be run at speeds in the MHz range before ever being sent to a fab. Booting an OS, running a complex multicore workload with shared memory, they can measure almost any workload. But this method is not available until late in the design phase and the boxes themselves are prohibitively expensive from being deployed very widely. The software models are the most useful for estimating performance, as long as they are written early and well :)

vintagedave 3y ago
> they create detailed software models (usually in C++) of their chips to estimate performance as closely as they can How does this work? Do they model at the transistor level, or at the level of logical functions, or..? I'm particularly curious how this can estimate performance if it's anything higher-level than a direct transistor-for-transistor, layout-aware, emulation. I'd be really interested in learning more if there's anything you could share, please. I can find info about chip design software and languages like Verilog (as you mention) but not this sort of modeling.
- nudgeee 3y ago
  When I was in chip design about 15 years ago, we did transaction level modeling (TLM) using SystemC. Not sure if it’s still a thing these days. https://en.m.wikipedia.org/wiki/Transaction-level_modeling https://en.m.wikipedia.org/wiki/Transaction-level_modeling
- amelius 3y ago
  Basically you model all the elements of a chip (queues, memory, alus, etc), and how much time they take. You use a virtual clock so your simulation model can run at a different pace.

synergy20 3y ago

systemc is a c++ derivative often used to model chip designs. Before chip tapeout most of the chip design has been fully simulated and emulated many many times, be it functional wise, or cycle by cycle(e.g. cycle accurate simulation).

andromeduck 3y ago
That just gave me PTSD. System C is terrible.
- synergy20 3y ago
  it's c++17 for me, I don't feel much difference at all between c++ and systemc.

epilys 3y ago

Arm has "Fast Models": https://developer.arm.com/Tools%20and%20Software/Fast%20Models https://developer.arm.com/Tools%20and%20Software/Fast%20Mode...

StillBored 3y ago
Those aren't for quantifying performance, they are for developing the firmware/OS/software stack to run on the platform. In other words, they are a slightly more accurate version of something like QEMU, although I guess I should point out they can generate traces that can be fed into tools to model HW perf, ex gem5.
- epilys 3y ago
  Second sentence in link: "They allow full control over the simulation, including profiling, debug and trace."