4 ms·
> SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in man
by imtringued 3y ago
> SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in many fewer gates than their earlier E cores.
How about SERV... That core can be configured to not use a register file (everything stored in BRAM).
- brucehoult 3y agoSiFive's 2-stage pipeline E20 (and Arm's Cortex M0+) still execute 1 instruction per clock cycle on straight line code -- they just take an extra cycle on any taken branch .. doesn't matter whether conditional, unconditional, call, return. SERV takes 32 clock cycles for most instructions, 64 cycles for some such as shifts and branches. Yes, there are some things SERV is fast enough for, but E20 is not all that much slower than 5-stage pipe plus branch prediction E31 -- E20 does 1.2 DMIPS/MHz compared to E31 1.6 (and Arm Cortex M0+ 0.95, M3/M4 1.25)
- Pet_Ant 3y ago> BRAM Never heard of this despite being casually interested in hardware, it is apparently this?: https://nandland.com/lesson-15-what-is-a-block-ram-bram/ https://nandland.com/lesson-15-what-is-a-block-ram-bram/
- OhMeadhbh 3y agoHa! Yes! The serial RV32 implementation! That was Olof Kindgren's design, right? It's another great design at one corner of the design space. I mentioned the SiFive core since that was the one I was most familiar with. I've heard Olaf speak at conferences. Smart guy.