3 ms·

FWIW, after listening to Chuck Peddle's CHM Oral History interview, I sort of realized I didn't need the ARM ecosystem and just designed my own 6-bit microcontr

FWIW, after listening to Chuck Peddle's CHM Oral History interview, I sort of realized I didn't need the ARM ecosystem and just designed my own 6-bit microcontroller. Granted, I'm only doing some very simple control applications and fabbing at 800nm, so it's not going to be competing with an i7 or an A72 anytime soon. IIRC, the RISC-V spec includes an "embedded profile" that specifies a CPU with 16 32-bit registers, so that should make RV32 even smaller than it would be otherwise. SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in many fewer gates than their earlier E cores. I worked at SiFive for a year and couldn't make sense of their product strategy. But maybe that's a me problem and not a SiFive problem. I really do sort of wonder what they're doing with 175m in Series F funding. Where do you go from there?

photonbeam 3y ago
Presumably lots of runway for salaries until next funding round or exit event
- OhMeadhbh 3y ago
  Intel publicly walked away from a $2B offer for SiFive, which means that at least one large chip manufacturer does not believe their IP is worth more than $2B. I'm not sure if the Round F post-money valuation was made public, but if it's more than $2B, SiFive will need to have a solid story for why a potential buyer should pay more than what Intel didn't want to pay. And if they're going to IPO, it would be helpful to have a reference customer for newer designs which seem to be on par with ARM offerings from four years ago. It's certainly not impossible, but it seems a tough row to hoe. But the cool part of this is that the ISA and many supporting packages (rocket, boom, etc.) are "open" and "free as in beer." Even if SiFive did fail, an IP investment in RISC-V would not necessarily have been a bad move. Which is why I said I'm fairly bullish on RISC-V (cause even if SiFive fails, customers existing investment in the ISA is not lost) but bearish on SiFive (because I fear their existing valuation may be too inflated.) I'm not trying to tell anyone their SiFive baby is ugly. I'm not saying designing a RISC-V solution is a bad move. I'm just saying from my perspective, with incomplete information about what's going on inside SiFive, it looks like they have a difficult road ahead. I would POSITIVELY WELCOME any information regarding reference customers or catalog parts which might imply there's a large customer who's signed on the dotted line to pay SiFive a royalty for using their designs. Full disclosure: I own no SIFIVE stock (or options) nor do I own stock in any company that competes in the RISC-V design space (Esperanto, Andes, Sandisk/WD, etc.) I still have stock in TXN though, but I haven't heard that they're deep in RISC-V. I am a former employee of SiFive, but was not employed in a management position; don't take my comments as being based on "inside information."
  - brucehoult 3y ago
    Intel walked away? It was my impression the Intel offer was unsolicited and it was SiFive who said "nah, not interested".
fidotron 3y ago
I don’t think it’s you. The only true thing that could be done is to have some top secret insight into CPU design optimization and apply it to RISC-V guiding the actual open spec along with you as necessary. Which is close to what Apple appear to have done with ARM64, but then Apple did hire/acquire an absolutely incredible team to get them there, and have the money to reward them.
- OhMeadhbh 3y ago
  Well... all the tech committees in the foundation report up through one of the SiFive principals, so if you want to change the spec, it at least appears SiFive has veto power.
imtringued 3y ago
> SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in many fewer gates than their earlier E cores. How about SERV... That core can be configured to not use a register file (everything stored in BRAM).
- brucehoult 3y ago
  SiFive's 2-stage pipeline E20 (and Arm's Cortex M0+) still execute 1 instruction per clock cycle on straight line code -- they just take an extra cycle on any taken branch .. doesn't matter whether conditional, unconditional, call, return. SERV takes 32 clock cycles for most instructions, 64 cycles for some such as shifts and branches. Yes, there are some things SERV is fast enough for, but E20 is not all that much slower than 5-stage pipe plus branch prediction E31 -- E20 does 1.2 DMIPS/MHz compared to E31 1.6 (and Arm Cortex M0+ 0.95, M3/M4 1.25)
- Pet_Ant 3y ago
  > BRAM Never heard of this despite being casually interested in hardware, it is apparently this?: https://nandland.com/lesson-15-what-is-a-block-ram-bram/ https://nandland.com/lesson-15-what-is-a-block-ram-bram/
- OhMeadhbh 3y ago
  Ha! Yes! The serial RV32 implementation! That was Olof Kindgren's design, right? It's another great design at one corner of the design space. I mentioned the SiFive core since that was the one I was most familiar with. I've heard Olaf speak at conferences. Smart guy.
taway32r41 3y ago
Here's a class at MIT that takes undergraduates who don't even know verilog and at then end of the class they have a mostly passable RV32I. Admittedly pushing that through VLSI CAD will not be push-button easy but many universities also have an undergraduate tape-out class, including MIT... https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/ https://ocw.mit.edu/courses/6-004-computation-structures-spr... Via MPW and assembly service one can easily have that die manufactured, packaged and mounted on custom PCBs for under $50K, a.k.a. much less than you'll pay in salary to have it designed, fabricated and tested. Even at non-American labor rates. In 2023 producing a computing core, albeit not a state-of-the-art one, is just not the moat it once was...
- OhMeadhbh 3y ago
  Yes. I saw that too. It turns out that "building a chip" is different than "building a chip that meets specfic requirements we got from the customer." I'm not saying "building a RV32x is impossible," I'm saying there are people with existing tool-chains that favour Verilog or SystemVerilog (or even VHDL, though I don't know of them personally.) And telling them "no, you should use Scala / Chisel / Firrtl to model the features you want to add to the system in order to meet customer requirements" is kind of a hard sell for many customers.
  - taway32r41 3y ago
    I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and is what matters. However, RISCV cores abound. In pretty much any HDL known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time. Not impossible, but it would be a significant investment, which is I guess SiFive's business model. Sell IP at prices cheaper than that. Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully. https://github.com/lowRISC/ibex https://github.com/lowRISC/ibex
brucehoult 3y ago
> couldn't make sense of their product strategy. But maybe that's a me problem Well, you drove a Bambino on a 60 miles each way commute over a huge hill, so there's something questionable going on there :p I can't see much wrong with the "start with microcontrollers, work your way up to single-issue Linux-capable, then dual-issue in-order, then small then bigger and bigger OoO" strategy. What else can you do? Try to take on Xeon day #1? On the other hand, sure, you can ask a lot of questions about how you take that to the market, and who the customers will be. SiFive early on obviously thought there were a lot of people out there who really wanted to make little custom chips for this and that but didn't have the skills, and SiFive (via buying OpenSilicon) could provide a one stop shop. And even provide a lot of automation around that, in the SiFive Chip Designer -- there used to be a web page (similar to SiFive Core Designer) but it's long gone, but see e.g. this Yunsup's presentation https://www.youtube.com/watch?v=pxd93jb1OAk https://www.youtube.com/watch?v=pxd93jb1OAk It seems no one really wanted to do that -- or at least SiFive didn't find them. So they got rid of OpenSilicon again (at a HUGE profit) and seem to be just selling CPU core IP to people who were already making chips, had all the people and knowledge to do that, but just wanted to change away from Arm or Tensilica or 8051 or whatever. > what they're doing with 175m in Series F funding. Where do you go from there? That's still absolute chickenfeed compared to what Intel or AMD or probably Arm spend on designing a single core.
- OhMeadhbh 3y ago
  Hey Bruce! I'm talking more about how they thought they were going to interact with customers w/ a design language no one seemed to want to use. I think we agree on that; NO ONE seemed to be asking for Rocket / Scala / Chisel / Firrtl and it seemed odd that every time a potential customer asked for Verilog, they kept pushing Chisel. But now that they're not pushing the core designer, how are they justifying their multiple? They're no longer a SaaS play, they're an IP design play which makes it a lot more difficult to hit the rule of 40. But Intel famously passed on the $2B offer, which means they have to do something to convince someone out there they ARE worth whatever their post-money, round F valuation is lest the round C investors lose money and the round A investors not make as much money as they had hoped. And yes $175m is less than ARM spends to design a core, but that's not what the $175m round F was for. Or at least I hope it's not what it's for, 'cause if they did sink it into designing a core that's just now on par with ARM's a72 (or was the recent goodness supposed to be on par with the a77?) from 4 years ago, what's the motivation for using a RISC-V core instead of an ARM core? "We're as good as ARM was 4 years ago" isn't a great marketing slogan. Your information about the details of the OpenSilicon spin-off must be better than mine. "Huge" profit is not what I heard. But neither of us were in San Mateo when that happened. I would LOVE to be able to buy a part that lets me test any of the recent cores (I mean for less than $100,000.) Or I would love to hear about any customers using the new cores. It shouldn't be that hard to find a reference customer.

photonbeam 3y ago

Presumably lots of runway for salaries until next funding round or exit event

OhMeadhbh 3y ago
Intel publicly walked away from a $2B offer for SiFive, which means that at least one large chip manufacturer does not believe their IP is worth more than $2B. I'm not sure if the Round F post-money valuation was made public, but if it's more than $2B, SiFive will need to have a solid story for why a potential buyer should pay more than what Intel didn't want to pay. And if they're going to IPO, it would be helpful to have a reference customer for newer designs which seem to be on par with ARM offerings from four years ago. It's certainly not impossible, but it seems a tough row to hoe. But the cool part of this is that the ISA and many supporting packages (rocket, boom, etc.) are "open" and "free as in beer." Even if SiFive did fail, an IP investment in RISC-V would not necessarily have been a bad move. Which is why I said I'm fairly bullish on RISC-V (cause even if SiFive fails, customers existing investment in the ISA is not lost) but bearish on SiFive (because I fear their existing valuation may be too inflated.) I'm not trying to tell anyone their SiFive baby is ugly. I'm not saying designing a RISC-V solution is a bad move. I'm just saying from my perspective, with incomplete information about what's going on inside SiFive, it looks like they have a difficult road ahead. I would POSITIVELY WELCOME any information regarding reference customers or catalog parts which might imply there's a large customer who's signed on the dotted line to pay SiFive a royalty for using their designs. Full disclosure: I own no SIFIVE stock (or options) nor do I own stock in any company that competes in the RISC-V design space (Esperanto, Andes, Sandisk/WD, etc.) I still have stock in TXN though, but I haven't heard that they're deep in RISC-V. I am a former employee of SiFive, but was not employed in a management position; don't take my comments as being based on "inside information."
- brucehoult 3y ago
  Intel walked away? It was my impression the Intel offer was unsolicited and it was SiFive who said "nah, not interested".

fidotron 3y ago

I don’t think it’s you. The only true thing that could be done is to have some top secret insight into CPU design optimization and apply it to RISC-V guiding the actual open spec along with you as necessary. Which is close to what Apple appear to have done with ARM64, but then Apple did hire/acquire an absolutely incredible team to get them there, and have the money to reward them.

OhMeadhbh 3y ago
Well... all the tech committees in the foundation report up through one of the SiFive principals, so if you want to change the spec, it at least appears SiFive has veto power.

imtringued 3y ago

> SiFive designed a dog-simple 2-stage pipeline 32 bit core that could even run without I-cache. I mean, it's not a speed demon, but it was implementable in many fewer gates than their earlier E cores. How about SERV... That core can be configured to not use a register file (everything stored in BRAM).

brucehoult 3y ago
SiFive's 2-stage pipeline E20 (and Arm's Cortex M0+) still execute 1 instruction per clock cycle on straight line code -- they just take an extra cycle on any taken branch .. doesn't matter whether conditional, unconditional, call, return. SERV takes 32 clock cycles for most instructions, 64 cycles for some such as shifts and branches. Yes, there are some things SERV is fast enough for, but E20 is not all that much slower than 5-stage pipe plus branch prediction E31 -- E20 does 1.2 DMIPS/MHz compared to E31 1.6 (and Arm Cortex M0+ 0.95, M3/M4 1.25)
Pet_Ant 3y ago
> BRAM Never heard of this despite being casually interested in hardware, it is apparently this?: https://nandland.com/lesson-15-what-is-a-block-ram-bram/ https://nandland.com/lesson-15-what-is-a-block-ram-bram/
OhMeadhbh 3y ago
Ha! Yes! The serial RV32 implementation! That was Olof Kindgren's design, right? It's another great design at one corner of the design space. I mentioned the SiFive core since that was the one I was most familiar with. I've heard Olaf speak at conferences. Smart guy.

taway32r41 3y ago

Here's a class at MIT that takes undergraduates who don't even know verilog and at then end of the class they have a mostly passable RV32I. Admittedly pushing that through VLSI CAD will not be push-button easy but many universities also have an undergraduate tape-out class, including MIT... https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/ https://ocw.mit.edu/courses/6-004-computation-structures-spr... Via MPW and assembly service one can easily have that die manufactured, packaged and mounted on custom PCBs for under $50K, a.k.a. much less than you'll pay in salary to have it designed, fabricated and tested. Even at non-American labor rates. In 2023 producing a computing core, albeit not a state-of-the-art one, is just not the moat it once was...

OhMeadhbh 3y ago
Yes. I saw that too. It turns out that "building a chip" is different than "building a chip that meets specfic requirements we got from the customer." I'm not saying "building a RV32x is impossible," I'm saying there are people with existing tool-chains that favour Verilog or SystemVerilog (or even VHDL, though I don't know of them personally.) And telling them "no, you should use Scala / Chisel / Firrtl to model the features you want to add to the system in order to meet customer requirements" is kind of a hard sell for many customers.
- taway32r41 3y ago
  I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and is what matters. However, RISCV cores abound. In pretty much any HDL known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time. Not impossible, but it would be a significant investment, which is I guess SiFive's business model. Sell IP at prices cheaper than that. Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully. https://github.com/lowRISC/ibex https://github.com/lowRISC/ibex

brucehoult 3y ago

> couldn't make sense of their product strategy. But maybe that's a me problem Well, you drove a Bambino on a 60 miles each way commute over a huge hill, so there's something questionable going on there :p I can't see much wrong with the "start with microcontrollers, work your way up to single-issue Linux-capable, then dual-issue in-order, then small then bigger and bigger OoO" strategy. What else can you do? Try to take on Xeon day #1? On the other hand, sure, you can ask a lot of questions about how you take that to the market, and who the customers will be. SiFive early on obviously thought there were a lot of people out there who really wanted to make little custom chips for this and that but didn't have the skills, and SiFive (via buying OpenSilicon) could provide a one stop shop. And even provide a lot of automation around that, in the SiFive Chip Designer -- there used to be a web page (similar to SiFive Core Designer) but it's long gone, but see e.g. this Yunsup's presentation https://www.youtube.com/watch?v=pxd93jb1OAk https://www.youtube.com/watch?v=pxd93jb1OAk It seems no one really wanted to do that -- or at least SiFive didn't find them. So they got rid of OpenSilicon again (at a HUGE profit) and seem to be just selling CPU core IP to people who were already making chips, had all the people and knowledge to do that, but just wanted to change away from Arm or Tensilica or 8051 or whatever. > what they're doing with 175m in Series F funding. Where do you go from there? That's still absolute chickenfeed compared to what Intel or AMD or probably Arm spend on designing a single core.

OhMeadhbh 3y ago
Hey Bruce! I'm talking more about how they thought they were going to interact with customers w/ a design language no one seemed to want to use. I think we agree on that; NO ONE seemed to be asking for Rocket / Scala / Chisel / Firrtl and it seemed odd that every time a potential customer asked for Verilog, they kept pushing Chisel. But now that they're not pushing the core designer, how are they justifying their multiple? They're no longer a SaaS play, they're an IP design play which makes it a lot more difficult to hit the rule of 40. But Intel famously passed on the $2B offer, which means they have to do something to convince someone out there they ARE worth whatever their post-money, round F valuation is lest the round C investors lose money and the round A investors not make as much money as they had hoped. And yes $175m is less than ARM spends to design a core, but that's not what the $175m round F was for. Or at least I hope it's not what it's for, 'cause if they did sink it into designing a core that's just now on par with ARM's a72 (or was the recent goodness supposed to be on par with the a77?) from 4 years ago, what's the motivation for using a RISC-V core instead of an ARM core? "We're as good as ARM was 4 years ago" isn't a great marketing slogan. Your information about the details of the OpenSilicon spin-off must be better than mine. "Huge" profit is not what I heard. But neither of us were in San Mateo when that happened. I would LOVE to be able to buy a part that lets me test any of the recent cores (I mean for less than $100,000.) Or I would love to hear about any customers using the new cores. It shouldn't be that hard to find a reference customer.