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I want to correct a recent post I made about the Vision Star Five. That board is only competitive against the Raspberry Pi 3. This one here actually is on a lev

I want to correct a recent post I made about the Vision Star Five. That board is only competitive against the Raspberry Pi 3. This one here actually is on a level playing field as the Raspberry Pi 4. https://sipeed.com/licheepi4a https://sipeed.com/licheepi4a In practice, the lack of vector instructions significantly limits the performance of the processors. So they tend to perform poorly in Geekbench or the Phoronix benchmarks. Anyway. The reason why RISC-V will beat ARM has little to do with the merits of RISC-V really. The reason is that ARM is a sclerotic company that is falling behind the competition and RISC-V as an architecture itself does nothing to beat ARM, it is the fact that everyone has become an ARM competitor that will finish off ARM. x86 is still a significant threat to both ARM and RISC-V in the datacenter, for instance because there is a semblance of competition between Intel and AMD.

RetroTechie 3y ago
Performance issues are 2-fold: a) As mentioned, vector extensions. If missing, big performance hit in some benchmarks. b) General software optimizations (compilers & GPU drivers in particular). A lot of these are still on the table. And thus situation should improve as software support matures further. Getting boards out there helps a lot. Developers can't fix software support without hardware to test on.
brucehoult 3y ago
Note that this board, the Lichee Pi 4A, has pretty good vector units, though they implement the current draft version of RVV (0.7.1) as at the time the core was designed in 2019. Significant incompatible changes were made before RVV 1.0 was ratified in November 2021 -- the general design is the same, most instructions and binary opcodes are the same, but both source code and binary incompatibilities exist. But at the same time, much useful library code such as memcpy(), strlen(), strcpy(), strcmp() etc can be binary compatible (and optimal) for both. Most toolchain and library effort is going into 1.0, of course, but if you buy one of these and want to write vectorised code you can do so using assembly language, which is much easier than using typical SIMD ISAs. For example, here is an optimised memcpy (dst, src, len in a0, a1, a2): 0000000000000000 <memcpy>: 0: 86aa mv a3,a0 0000000000000002 <.L1^B1>: 2: 00267757 vsetvli a4,a2,e8,m4,d1 6: 12058007 vlb.v v0,(a1) a: 95ba add a1,a1,a4 c: 8e19 sub a2,a2,a4 e: 02068027 vsb.v v0,(a3) 12: 96ba add a3,a3,a4 14: f67d bnez a2,2 <.L1^B1> 16: 8082 ret

RetroTechie 3y ago

Performance issues are 2-fold: a) As mentioned, vector extensions. If missing, big performance hit in some benchmarks. b) General software optimizations (compilers & GPU drivers in particular). A lot of these are still on the table. And thus situation should improve as software support matures further. Getting boards out there helps a lot. Developers can't fix software support without hardware to test on.

brucehoult 3y ago

Note that this board, the Lichee Pi 4A, has pretty good vector units, though they implement the current draft version of RVV (0.7.1) as at the time the core was designed in 2019. Significant incompatible changes were made before RVV 1.0 was ratified in November 2021 -- the general design is the same, most instructions and binary opcodes are the same, but both source code and binary incompatibilities exist. But at the same time, much useful library code such as memcpy(), strlen(), strcpy(), strcmp() etc can be binary compatible (and optimal) for both. Most toolchain and library effort is going into 1.0, of course, but if you buy one of these and want to write vectorised code you can do so using assembly language, which is much easier than using typical SIMD ISAs. For example, here is an optimised memcpy (dst, src, len in a0, a1, a2): 0000000000000000 <memcpy>: 0: 86aa mv a3,a0 0000000000000002 <.L1^B1>: 2: 00267757 vsetvli a4,a2,e8,m4,d1 6: 12058007 vlb.v v0,(a1) a: 95ba add a1,a1,a4 c: 8e19 sub a2,a2,a4 e: 02068027 vsb.v v0,(a3) 12: 96ba add a3,a3,a4 14: f67d bnez a2,2 <.L1^B1> 16: 8082 ret