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> All RISC-V architectures use 32 general purpose registers (GPRs) Strictly speaking this is incorrect. There are variants called rv32e/rv64e which have 16 gen

> All RISC-V architectures use 32 general purpose registers (GPRs) Strictly speaking this is incorrect. There are variants called rv32e/rv64e which have 16 general purpose registers. These are particularly nice as a VM ISA since the reduced number of registers allows you to JIT the code to AMD64 (which itself only has 16 GPRs) without having to spill the registers.

hasheddan 3y ago
Author here -- that is a great call out, thanks for the correction!
bpye 3y ago
There are some MCUs that use RV32E also - the CH32V003 [0] comes to mind. [0] - https://github.com/openwch/ch32v003 https://github.com/openwch/ch32v003
bonzini 3y ago
In practice you will need some extra state, for example the RISC-V program counter and the x86 stack, so it's not really possible to map registers 1:1. Also some instructions on x86 need extra registers, or they can only refer to fixed registers (e.g. EAX and EDX for multiply-high).
- kouteiheika 3y ago
  > so it's not really possible to map registers 1:1 Oh it's definitely possible. I know this because I'm writing such a VM right now. (: But I should have been a little more precise, sorry. By "without having to spill the registers" I didn't mean that you don't have to ever temporarily push anything to the stack, just that you can keep all of the RISC-V registers in native AMD64 registers all the time instead of having to keep some of them in memory (which you'd have to do with a full fat 32-register RISC-V ISA). In general with rv32e/rv64e at most you only need 15 registers because one of the registers is the zero register. This allows you to assign every RISC-V register to an AMD64 register and keep rsp for the native stack. And if you only want to support bare metal userspace RISC-V code with normal ABI then it gets even easier because you only need 13 registers (gp and tp will be unused), so you'll have two extra temporary AMD64 registers to use. > Also some instructions on x86 need extra registers, or they can only refer to fixed registers (e.g. EAX and EDX for multiply-high). Yes. For example, the shift instruction hardcodes the shift amount in rcx. For the 15 register RISC-V you'll push rcx temporarily to the stack, and pop it after the shift, and for the 13 register RISC-V you can just designate rcx as one of your temporary registers, so you only need an extra mov here. Or you can use the shift instruction from BMI2, which doesn't hardcode the register. There are ways to handle these.

hasheddan 3y ago

Author here -- that is a great call out, thanks for the correction!

bpye 3y ago

There are some MCUs that use RV32E also - the CH32V003 [0] comes to mind. [0] - https://github.com/openwch/ch32v003 https://github.com/openwch/ch32v003

bonzini 3y ago

In practice you will need some extra state, for example the RISC-V program counter and the x86 stack, so it's not really possible to map registers 1:1. Also some instructions on x86 need extra registers, or they can only refer to fixed registers (e.g. EAX and EDX for multiply-high).

kouteiheika 3y ago
> so it's not really possible to map registers 1:1 Oh it's definitely possible. I know this because I'm writing such a VM right now. (: But I should have been a little more precise, sorry. By "without having to spill the registers" I didn't mean that you don't have to ever temporarily push anything to the stack, just that you can keep all of the RISC-V registers in native AMD64 registers all the time instead of having to keep some of them in memory (which you'd have to do with a full fat 32-register RISC-V ISA). In general with rv32e/rv64e at most you only need 15 registers because one of the registers is the zero register. This allows you to assign every RISC-V register to an AMD64 register and keep rsp for the native stack. And if you only want to support bare metal userspace RISC-V code with normal ABI then it gets even easier because you only need 13 registers (gp and tp will be unused), so you'll have two extra temporary AMD64 registers to use. > Also some instructions on x86 need extra registers, or they can only refer to fixed registers (e.g. EAX and EDX for multiply-high). Yes. For example, the shift instruction hardcodes the shift amount in rcx. For the 15 register RISC-V you'll push rcx temporarily to the stack, and pop it after the shift, and for the 13 register RISC-V you can just designate rcx as one of your temporary registers, so you only need an extra mov here. Or you can use the shift instruction from BMI2, which doesn't hardcode the register. There are ways to handle these.