4 ms·

I wish people would stop quoting marketing material as some kind representation of what they know. You're giving completely the wrong impression about dsp slic

I wish people would stop quoting marketing material as some kind representation of what they know. You're giving completely the wrong impression about dsp slices - it is absolutely not 1 dsp slice per FP operator at any precision that you would want to do floating point arithmetic. It's definitely at least 2 plus a whole bunch of LUTs (~500) for FP16 with 4 stages or something like that. And if you want faster (fewer stages) then you need more slices. On alveo u280, which is an ultrascale part, I have never been able to effectively utilize more than ~4000 dsp slices (out of 9024) for 5,4 mults and that cost basically 99% of clbs in SLR1 and SLR2. And even then, disconnected FPUs are completely meaningless without a datapath implementing eg matmul and boy oh boy do you have no clue what you're in for there. Takeaway: it's pointless to compare raw specsheet numbers when everything comes down to datapath.

gsmecher 3y ago
> everything comes down to datapath. Ain't that the truth. However: Xilinx's DSP58 blocks (Versal devices), and older Intel DSPs, do integrate floating point into the DSP tiles - which does narrow the gap between the datasheet's DSP count and the number of floating-point operations achievable per clock.
- mathisfun123 3y ago
  > Xilinx's DSP58 blocks (Versal devices) this is correct (i am currently working on designs that target these parts) but those things are more expensive than comparably sized/equipped nvidia gpus so (in the context of this discussion) it's moot.
  - rzzzt 3y ago
    Ballas mentions in a neighboring reply that the eGPU from the paper is using an Agilex 7: https://ark.intel.com/content/www/us/en/ark/products/217645/intel-agilex-7-fpga-fseries-014-r24b.html https://ark.intel.com/content/www/us/en/ark/products/217645/...
    - mathisfun123 3y ago
      Yes but as you can see by reading, this comment chain starts with someone linking to a xilinx product
Ballas 3y ago
The Intel Agilex (that was used in this paper) DSP blocks natively support single and half precision floating point.

gsmecher 3y ago

> everything comes down to datapath. Ain't that the truth. However: Xilinx's DSP58 blocks (Versal devices), and older Intel DSPs, do integrate floating point into the DSP tiles - which does narrow the gap between the datasheet's DSP count and the number of floating-point operations achievable per clock.

mathisfun123 3y ago
> Xilinx's DSP58 blocks (Versal devices) this is correct (i am currently working on designs that target these parts) but those things are more expensive than comparably sized/equipped nvidia gpus so (in the context of this discussion) it's moot.
- rzzzt 3y ago
  Ballas mentions in a neighboring reply that the eGPU from the paper is using an Agilex 7: https://ark.intel.com/content/www/us/en/ark/products/217645/intel-agilex-7-fpga-fseries-014-r24b.html https://ark.intel.com/content/www/us/en/ark/products/217645/...
  - mathisfun123 3y ago
    Yes but as you can see by reading, this comment chain starts with someone linking to a xilinx product

Ballas 3y ago

The Intel Agilex (that was used in this paper) DSP blocks natively support single and half precision floating point.