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My understanding is that, while double pumped 512 bit makes sense from AMD from a compatibility perspective, it's not a great solution. The sheer amount of arch
by mort96 3y ago
My understanding is that, while double pumped 512 bit makes sense from AMD from a compatibility perspective, it's not a great solution. The sheer amount of architectural stare you need to keep track of with all these 512 bit instructions gets unwieldy, especially on smaller cores, and there's no real performance advantage to double pumped 512 vs normal 256.
This new ISA seems to include 256 bit versions of the instructions which were previously only in AVX-512 though. That's exciting.
- adrian_b 3y agoActually on Zen 4 using 512-bit instructions instead of 256-bit instructions frequently improves the performance a lot, despite using the same execution units. The reason is that in Zen 4 the relatively narrow instruction decoder is frequently the bottleneck, so twice less instructions can influence the speed very much. On future CPUs that will be able to decode more instructions in parallel, like Zen 5 and the future Intel CPUs, 512-bit instructions might no longer increase the speed when the width of the execution units remains of 256 bits, so perhaps even AMD may introduce a split between laptop CPUs that implement only the 256-bit subset of AVX-512 rebranded AVX10 and server CPUs that implement the full AVX-512 a.k.a. AVX10.
- Dylan16807 3y agoThe architectural state is quadrupled, but the real impact is much smaller. Single-pumped AVX2 implementations already had ~150 extra 256-bit registers for pipelining purposes. And if you're double pumping 512-bit instructions, then you can pipeline just as deep without changing the quantity or width. Maintaining similar performance is not 512B->2KB, it's 5KB->7KB. (But note that the E cores are largely double-pumping 256 bit instructions already, so for them it's a big change.)