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Why should it produce those designs? Are they in any known sense optimal?

sitkack 3y ago
I don't think any reviewer of the paper would ask why they didn't use one the processors mentioned. I think of lots of reasons to do it with a riscv * lots of excellent simulators and emulators * great tool chains * both software (Verilog, VHDL) implementations as well as hardware * regular, compact instruction set (no condition codes) Using anything besides RISC-V would have been an order of magnitude harder.
bsder 3y ago
> Why should it produce those designs? Are they in any known sense optimal? Yes. 6502 was quite cheap for the day so is much more optimal for cost than most designs. The 6809 was done fixing the mistakes of the 6800 and it's implementation is much more orthogonal. The 6800 and 8051 are probably the best documented. All of them have extremely long lived tool chains and support. Pick your optimality. In addition, then "Why should it produce a RISC-V design?" RISC-V is definitely sub-optimal on quite a few fronts. If a system is doing actual CPU design, as claimed by the paper, those designs (6502, 6809, 8051) are a simple sanity check. The designs are extensively documented to the point that we have web pages that simulate them down to the transisitor. You should be able to provide a "relatively" small input and get back a compatible design as an output. A 6502 has only 3500 or so transistors. That's on the order of the complexity they claim in the paper. This would prevent someone like me from saying: "You basically stuffed a RISC-V design into the training set, managed to launder it through ML/AI to get the computer to cough it back up, then deployed a legion of humans to patch the result suffciently that it could be called "Linux compatible", and finally barfed out a publication with 6 pages of link references in a 12 page paper." Here's the touchstone for whether AI is doing chip design: "When AI can distinguish between control plane and datapath and synthesize and place them differently, AI is doing actual design."
- calf 3y ago
  The title is very inaccurate. The abstract is also misleading, their design is not even pipelined (in the paper they claim only preliminary results for a 2-stage pipeline). This is unfortunate because their idea of using BDDs--which are studied extensively in hardware design automation--is a fair paper on its own. Nevertheless, the claims about design are inexcusable and any of the cited authors, many of whom are experts in CAD, would object to such abuse of accepted terminology.

I don't think any reviewer of the paper would ask why they didn't use one the processors mentioned. I think of lots of reasons to do it with a riscv * lots of excellent simulators and emulators * great tool chains * both software (Verilog, VHDL) implementations as well as hardware * regular, compact instruction set (no condition codes) Using anything besides RISC-V would have been an order of magnitude harder.

bsder 3y ago

> Why should it produce those designs? Are they in any known sense optimal? Yes. 6502 was quite cheap for the day so is much more optimal for cost than most designs. The 6809 was done fixing the mistakes of the 6800 and it's implementation is much more orthogonal. The 6800 and 8051 are probably the best documented. All of them have extremely long lived tool chains and support. Pick your optimality. In addition, then "Why should it produce a RISC-V design?" RISC-V is definitely sub-optimal on quite a few fronts. If a system is doing actual CPU design, as claimed by the paper, those designs (6502, 6809, 8051) are a simple sanity check. The designs are extensively documented to the point that we have web pages that simulate them down to the transisitor. You should be able to provide a "relatively" small input and get back a compatible design as an output. A 6502 has only 3500 or so transistors. That's on the order of the complexity they claim in the paper. This would prevent someone like me from saying: "You basically stuffed a RISC-V design into the training set, managed to launder it through ML/AI to get the computer to cough it back up, then deployed a legion of humans to patch the result suffciently that it could be called "Linux compatible", and finally barfed out a publication with 6 pages of link references in a 12 page paper." Here's the touchstone for whether AI is doing chip design: "When AI can distinguish between control plane and datapath and synthesize and place them differently, AI is doing actual design."

calf 3y ago
The title is very inaccurate. The abstract is also misleading, their design is not even pipelined (in the paper they claim only preliminary results for a 2-stage pipeline). This is unfortunate because their idea of using BDDs--which are studied extensively in hardware design automation--is a fair paper on its own. Nevertheless, the claims about design are inexcusable and any of the cited authors, many of whom are experts in CAD, would object to such abuse of accepted terminology.