5 ms·
The most interesting part is that we are also seeing the opposite happen. SoCs are integrating more and more specialized functionality into one chip, rather tha
by crote 3y ago
The most interesting part is that we are also seeing the opposite happen. SoCs are integrating more and more specialized functionality into one chip, rather than depending on external hardware for it.
Modern mobile phones essentially have everything except memory and storage in a single chip, the Northbridge died a decade ago, and recent Zen chips can even function without a Southbridge.
- dikei 3y agoYup, and Apple SoC already have the DRAM packaged together with the CPU, only the SSD is left out now.
- corvettez0606 3y agoApple did a lot right with this change to make memory fast. I can see AMD and Intel adopting a similar strategy and putting something like 16 GB of dram on chip. Need more than that? Then add “L2 dram” on an external dimm. 16 GB will cover most people’s use cases and with the ability to add L2 dram the high memory usage cases are covered too. (I remember when you could buy cards with L2 cache on them back in the day. 486 I think had them. This is just taking it to the next level.)
- ZiiS 3y agoAll modem CPUs have L1, L2, and L3 caches. Commonly available consumer chips go up to 144MB already.
- pulse7 3y agoParent is not speaking about cache (L1/L2/L3/...), but about main memory (RAM) of which 16GB would be permanently integrated into the CPU - this would be L1 RAM and of the rest, L2 RAM which would be outside of CPU.
- bee_rider 3y agoI’m not exactly sure why they mentioned it, but in their defense—it is all fundamentally volatile storage, just used differently. Memory of course has a special magical meaning to operating systems, but hypothetically it might make sense to mark L3 cache as memory, and maybe… treat DRAM as swap? Hypothetically!
- pulse7 3y ago"L3 cache" is a cache of what then? (SWAP stores only parts of memory, not all...)
- bee_rider 3y agoIt wouldn’t be a cache anymore in that case. The hardware thing is named after the typical job we have for it, but if we want to play with the idea of changing how things are used the names might not line up perfectly anymore. It’s all volatile storage with different uses.
- tjoff 3y agoMaybe for ultrabooks and similar but I'm not overly thrilled about the idea. Is there a good overview of how much of a benefit the onchip ram is?
- yvdriess 3y agoNot an Apple innovation. Intel already launched a processor with 16GB on-package MCDRAM in 2016 (Knight's Landing Xeon Phi). You can even buy an Intel Xeon with 64GB HBM2 today. Nvidia likewise has been packaging HBM with their server GPUs. Embedded DRAM (eDRAM) been used for long time in the mobile and console space. e.g. IBM's POWER7 (e.g. Nintendo Gamecube) and Intel Haswell products. However, using a logic process node to make DRAM cells is wasteful. Packaging technologies have advanced sufficiently that you now regularly see regular DRAM dies (LPDDR, HBM) being put on-package. But all of that is packaging and manufacturing technologies. We're still taking to DRAM over a memory bus like we're still living in the '80s. The true innovation I'm looking out for is for a company to stick its neck out and use a different communication standard to talk with the DRAM modules. Something like the CLX.mem standard, which is used in the server space to talk to memory expansion modules.
- kuschku 3y ago"16GB will cover most people's use cases" may be true, but DIMMs will also cover most people's performance needs. The amount of people that need memory speeds and latencies beyond what SO-DIMM and CAMM can handle, but only need 16GB of RAM is absolutely tiny.
- PedroBatista 3y agoAnd when it ceases to be sufficient, just discard it and purchase a replacement. How convenient.
- _8j50 3y agoLast I checked radio controllers like wifi,nfc and bluetooth were not on SoC. Has that changed? Because I used to desolder those chips to reduce phones' functionality.
- tremon 3y agorecent Zen chips can even function without a Southbridge Does this mean the processors have built-in USB and PCI controllers? Or is this more a case of "if you don't need many peripherals, you can do without a southbridge"? I suspect the reason they can do without the southbridge is because many high-speed connections are PCIe these days (including storage and networking). But I don't see a good reason why Zen would have on-chip USB or RS232 controllers.
- glowingly 3y agoThey have USB controllers and enough PHYs for 4 USB 3.x ports on AM4. I don't know about serial, but they did have SPI and I2C. AM5, I don't know.
- crote 3y agoYes they do! Socket AM5 has an integrated x16 PCIe bus, three x4 PCIe buses (one usually used for the chipset, one for NVMe, and one for USB4 ports - but other assignments are of course possible), a dedicated DisplayPort connection, a three-port hybrid USB3/DisplayPort interface, a dedicated USB3 connection, SMBus & I3C, and a HDA/SoundWire connection. The AM5 Southbridge is essentially just a PCIe hub combined with some PCIe-to-USB and PCIe-to-SATA interfaces. If you don't need those, you can just leave it out! In practice you'll virtually always have it for the SATA ports and extra PCIe lanes, though. Don't forget that USB is also a high-speed connection these days. 10Gbps is very common, and USB4 goes up to 40Gbps in Gen3 - with 80Gbps for Gen4 on the way. RS232 is indeed not included, but that's pretty much a dead port anyways: no reason to use it for onboard peripherals, and consumer motherboards rarely have a header for it these days.
- myself248 3y agoWould it be say that they're converging on a particular die size? i.e. CPUs need to be huge to achieve their performance targets, but wafer defects make for poor margins with chips that large, so they split up into chiplets to allow mixing and matching of good parts. But SOCs are nowhere near that limit yet, so their tiny dies are growing to bring more more functionality on-die and reap the benefits of integration.
- cubefox 3y agoThat seems plausible, although mobile SoCs are much more optimized for power efficiency (roughly, FLOP per watt), while other chips are more optimized for price/performance (roughly, FLOP/s per chip price). When the latter stops improving, when the cost per transistor goes up, then shrinking structures could still make sense for mobile SoCs, insofar efficiency still improves. This would result in smaller mobile SoCs. But this wouldn't affect other chips which aren't similarly power constrained.
- myself248 3y agoOooo, speaking of power, I've heard a few mentions about the power it takes to move a single bit on-die versus off-die (down in the femtojoules and stuff, but it does add up). I wonder if that's it; simply keeping a PCIe link awake between various chips uses a bit of power to drive the trace capacitance, for instance.
- bunabhucan 3y agoEpyc does not use a chipset, threadripper on down is nerfed epyc with less cpus, memory and/or pcie lanes exposed. The motherboard chip on the nerfed versions is just a second i/o die like on the cpu. https://en.wikipedia.org/wiki/Epyc#Design https://en.wikipedia.org/wiki/Epyc#Design