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Some risc-v chips can execute in order and avoid having spectre-like problems. I work at a IaaS where customers deploy through our hosted cicd and we are very i

Some risc-v chips can execute in order and avoid having spectre-like problems. I work at a IaaS where customers deploy through our hosted cicd and we are very interested in risc-v solving our multi-tenancy concerns. GCC and clang already have enough support for risc-v that we have no concerns for support being there. If GCC and clang have what's necessary, everything else is fine. The moment we see close to a juncture where we can put an order in for risc-v with very many cores, our investors are going to dump a massive round of funding. Whether risc-v is popular or not doesn't matter. Our multi-tenant services won't have fundamental security isolation problems, everyone serving on x86_64 and ARM will. Looks like risc-v will dominate where things actually matter, unless some new iteration of OpenPOWER comes out.

gjsman-1000 3y ago
> don't have spectre-like problems You could just disable out-of-order execution but there’s a major performance hit. Some simpler ARM designs don’t have speculative execution.
jeffbee 3y ago
> Risc-v chips execute in order Odd then that the one of the first RISC-V hardware implementations called itself "Berkeley Out-of-Order Machine".
- brucehoult 3y ago
  What the person said was "SOME risc-v chips can execute in order". In fact the vast vast majority of RISC-V chips shipped to date are in-order, including the JH7110 SoC in this year's VisionFive 2, Star64 and PineTab-V, and Milk-V Mars. The only shipping OoO RISC-V chips are the TH1520 and SG2042 with C910 cores, as used in the Sipeed LicheePi4A and Milk-V Pioneer boards. BOOM was (and is) an experimental university project, not a product. But as Jim Keller said in a recent interview "with RISC-V a couple of university students created an OoO core that was better than the first Intel i7s which hundreds of engineers worked on".
  - jeffbee 3y ago
    That's a revision. The comment originally made the blanket statement that RISC-V executes in order.
    - brucehoult 3y ago
      Ok, I didn't see that. It's true for 99.99999% of currently-deployed RISC-V cores but, since the TH1520 and SG2042 boards started shipping in May, not 100% any more.
tails4e 3y ago
I don't think in order is related to the ISA. There may be a guarantee of the order of operations when it comes to the view of memory the programmer sees, but that does not prevent the hardware from executing out of order, as long as the end result is the same. X86 has strict memory ordering also, but both intel and AMD use out of order at the hardware level
monocasa 3y ago
Most of the server chips I've seen coming down the pipe (Tenstorrent, Ventana, Rivos) are all relatively standard OoO cores. The XuanTie c910 in the Alibaba chips are simpler, but OoO cores as well.
willis936 3y ago
How is speculative execution inherently insecure?
- sulam 3y ago
  Because it leads to timing attacks as an immediate next issue.
  - panick21_ 3y ago
    That's not inherent.
    - sulam 3y ago
      So we’re going to speculatively execute some code and then not speed anything up? I mean, theoretically yes but practically isn’t that the point?
      - panick21_ 3y ago
        The relevant question is if any information leaks to the other processes. And that can be prevent if you take care in your processor design.
    - user6723 3y ago
      The timing attacks result in data leakage between processes, even if the processes are in different VMs. It's a huge problem for cloud providers, but most customers don't fully understand the issue and cloud providers aren't forthcoming that "mitigations" are partial at best, so it's really just a huge problem for cloud customers.
      - willis936 3y ago
        Yes but how are the timing attacks an inherent vulnerability and not the result of an accounting error? If the bookkeeping is done properly and the correct amount of cleanup time on a speculated branch is done I don't see how adjacent processes would leak data.
wbl 3y ago
Architecture does not determine microarchitecture like speculation. The BOOM is designed to speculate, and there are anti-spectre protections chips can use.
photonbeam 3y ago
SiFive makes OoO cores for riscv
imtringued 3y ago
Isn't encrypted memory a better strategy for multi tenancy? Also, why not have dedicated CPUs per customer? Designing a RISCV CPU for multi tenancy shouldn't be impossible regardless of whether it uses out of order execution or not.

gjsman-1000 3y ago

> don't have spectre-like problems You could just disable out-of-order execution but there’s a major performance hit. Some simpler ARM designs don’t have speculative execution.

jeffbee 3y ago

> Risc-v chips execute in order Odd then that the one of the first RISC-V hardware implementations called itself "Berkeley Out-of-Order Machine".

brucehoult 3y ago
What the person said was "SOME risc-v chips can execute in order". In fact the vast vast majority of RISC-V chips shipped to date are in-order, including the JH7110 SoC in this year's VisionFive 2, Star64 and PineTab-V, and Milk-V Mars. The only shipping OoO RISC-V chips are the TH1520 and SG2042 with C910 cores, as used in the Sipeed LicheePi4A and Milk-V Pioneer boards. BOOM was (and is) an experimental university project, not a product. But as Jim Keller said in a recent interview "with RISC-V a couple of university students created an OoO core that was better than the first Intel i7s which hundreds of engineers worked on".
- jeffbee 3y ago
  That's a revision. The comment originally made the blanket statement that RISC-V executes in order.
  - brucehoult 3y ago
    Ok, I didn't see that. It's true for 99.99999% of currently-deployed RISC-V cores but, since the TH1520 and SG2042 boards started shipping in May, not 100% any more.

tails4e 3y ago

I don't think in order is related to the ISA. There may be a guarantee of the order of operations when it comes to the view of memory the programmer sees, but that does not prevent the hardware from executing out of order, as long as the end result is the same. X86 has strict memory ordering also, but both intel and AMD use out of order at the hardware level

monocasa 3y ago

Most of the server chips I've seen coming down the pipe (Tenstorrent, Ventana, Rivos) are all relatively standard OoO cores. The XuanTie c910 in the Alibaba chips are simpler, but OoO cores as well.

willis936 3y ago

How is speculative execution inherently insecure?

sulam 3y ago
Because it leads to timing attacks as an immediate next issue.
- panick21_ 3y ago
  That's not inherent.
  - sulam 3y ago
    So we’re going to speculatively execute some code and then not speed anything up? I mean, theoretically yes but practically isn’t that the point?
    - panick21_ 3y ago
      The relevant question is if any information leaks to the other processes. And that can be prevent if you take care in your processor design.
  - user6723 3y ago
    The timing attacks result in data leakage between processes, even if the processes are in different VMs. It's a huge problem for cloud providers, but most customers don't fully understand the issue and cloud providers aren't forthcoming that "mitigations" are partial at best, so it's really just a huge problem for cloud customers.
    - willis936 3y ago
      Yes but how are the timing attacks an inherent vulnerability and not the result of an accounting error? If the bookkeeping is done properly and the correct amount of cleanup time on a speculated branch is done I don't see how adjacent processes would leak data.

wbl 3y ago

Architecture does not determine microarchitecture like speculation. The BOOM is designed to speculate, and there are anti-spectre protections chips can use.

photonbeam 3y ago

SiFive makes OoO cores for riscv

imtringued 3y ago

Isn't encrypted memory a better strategy for multi tenancy? Also, why not have dedicated CPUs per customer? Designing a RISCV CPU for multi tenancy shouldn't be impossible regardless of whether it uses out of order execution or not.