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Are chiplets enough to save Moore’s Law?
- bee_rider 3y agoWhere are R&D nodes at nowadays, anyway? I guess chiplets will help with yield issues, which could make some nodes economical (which is of course what Moore’s law is all about). But of course they won’t allow them to get down to transistor sizes that they just couldn’t hit at all.
- tux1968 3y agoJim Keller is bullish on chiplets and it's not just about yield, it's also about power efficiency and the economics of only using the most expensive nodes (eg. 3nm) for critical parts and being able to combine it lego-style with IP fabricated on cheaper nodes. https://youtu.be/c_Wj_rNln-s?t=127 https://youtu.be/c_Wj_rNln-s?t=127
- bee_rider 3y agoThat’s interesting, I’m curious about the argument for power efficiency (it seems like breaking a design up into chiplets would only hurt there, but I’m no Jim Keller!). I’ll definitely check the video out when I get a chance. Lego-ing out IP blocks could be really cool. It would be neat if this gave OEMs room to compete in a more technical field (selling Xeons in Dell cases vs Xeons in Lenovo cases is not very cool, if Dell and Lenovo could pick the parts in their package, that could be interesting).
- pclmulqdq 3y agoI think this may be where some manufacturers are heading, but not necessarily the big "consumer" names like Intel/AMD. It's a way to significantly lower the risk of building an SoC, and I think it's more plausible that this sort of third-party chiplet market will be driven by the Marvell/Broadcom types rather than Intel/AMD.
- touisteur 3y agoThere was something impressive with tenstorrent original architecture (haven't been following the talk about pivoting to risc-v) was the low cost of validation. It seemed like the idea was 'cheapest to tape-out with max FLOPS' and it somehow worked out well. Can't say more, I couldn't ever get my hands on one of them Grayskull so...
- pclmulqdq 3y agoQuietly, digital ASIC validation has gotten very cheap and quick over the last 20 years thanks to the proliferation of software models and compilers that translate Verilog to C++ (which are literally orders of magnitude faster than previous simulators). I'm not surprised that Tenstorrent has been doing well with that, given the expertise they have.
- ksec 3y agoI am not sure where power efficiency came from, both AMD and Intel along with TSMC were very clear it was not about power efficiency, whether that is the current AMD Chiplet or CoWoS ( TSMC ) / EMIB ( Intel ).
- tux1968 3y agoThe linked video above makes his assertion pretty clear. If you can move items that were previously off-chip onto a chiplet, you've shortened the interconnect traces and can increase speed and reduce power consumption. In his particular case, the hope is to combine CPU, AI, and IO chiplets into the same package.
- BeefWellington 3y agoIn a way, these points are roughly how modern computers work. For instance, let's say you bought a new PC in 2017 with a high end graphics card. Your CPU was probably manufactured on 14nm processes, your GPU on 16nm, your RAM from 16 to 20nm, and your motherboard chipset on 22nm. It's been a similar story throughout computing. Taking that idea and scaling it down to processor designs themselves is cool and no doubt faces hard technical challenges.
- uluyol 3y agoIt's also about reuse and fungibility. AMD has used the same IO die across multiple generations of Zen hardware. This cuts the dev and validation costs for using new processes. Fungibility helps reduce the cost of making SKUs. Want more cores? Add more compute dies. Your customers want more big chips then expected? It's easier/faster to adapt production since only the final steps differ. The component pieces are the same.
- ksec 3y agoExcept the cost of advance packaging isn't cheap. So while you save on validation , yield and multi use of component you are trading those with much higher cost of packaging. Although CoWoS being a must have for all future HPC AI requirement I assume we could drive down the cost relatively quickly. But I still have doubt in certain market segment whether this make sense, especially those in the lower end market.
- bena 3y agoWho cares? Moore's Law is not something that needs "saving". It was an observation of the time. It was bound to run up against physical reality. In 1965, he predicted a doubling of components every year for the next ten years. In 1975, he changed it to every 2 years. And he was probably only looking out to the next 10 to 20 years. Because, you know, that's reasonable. Even Moore himself knew that it was impossible to continue indefinitely. Yes, let's get better. Yes, let's try to find more ways to efficiently compute. But let's not be slaves to words spoken before we were born because they were easy to achieve back then.
- wmf 3y agoNividia is using "the end of Moore's Law" as an excuse to provide zero price/performance improvement. It would be pretty anti-consumer if that became the industry standard.
- dolni 3y agoI'm sure AMD would LOVE to eat Nvidia's lunch.
- wmf 3y agoYet they're not. They're selling very few GPUs at high prices.
- Buttons840 3y agoIs that because they have bad hardware or because of the CUDA monopoly?
- wmf 3y agoNeither?
- gymbeaux 3y agoMore the latter than the former these days, but at a macro level, like last 20 years, it’s more the former than the latter. Basically AMD has caught up (arguable, but let’s say they have) to Nvidia with respect to driver quality and hardware performance/power consumption, just in time for the world to become more concerned with how a GPU handles AI stuff than how it handles video games.
- Animats 3y agoIn the transistors per cubic meter dimension, maybe. In the cost and heat dimensions, no.
- bee_rider 3y agoChiplets should help keep the yields up (I assume, at least, that they test the chiplets before packing them in together into the package, although that’s a guess). Improving yields should help with prices; throwing away products or binning them down isn’t very economically favorable.
- hristov 3y agoYes they do. In fact chiplets are bringing a lot of excitement to the semi testing industry. Chiplets have popularized the concept of “known good die”. I.E. a chiplet that has been tested so much that is practically proven to be error free. This is necessary because packaging chiplets is usually nonreversible. So if you put ten chiplets in a package and one of them is bad, you have to toss the entire package with all ten chiplets and all your packaging costs.
- anyoneamous 3y agoBetteridge alert!
- AnimalMuppet 3y agoWhere do chiplets fit in Moore's Law? Moore said that the number of transistors in a single package would increase. Well, are chiplets their own package? If so, then Moore's Law is clearly broken, because they are a decrease in the number of transistors in a package (compared to conventional approaches). But if you don't consider a chiplet to be an independent package, then yes, maybe they can save Moore's Law. Personally, once chiplets enter the picture, I think the question is becoming one of semantics, and therefore less interesting.
- ilyt 3y ago>Where do chiplets fit in Moore's Law? Moore said that the number of transistors in a single package would increase. Well there were no multi-chiplet IC's back in his days
- polishdude20 3y agoI wonder if / when hardware can't continue to get better, will software start to then be the differentiating factor in performance?
- BenoitP 3y agoIt sure can. Large parts of the whole stack have been developed with trading off developer velocity vs performance. But hardware still has plenty of runway. The third dimension is barely beginning. Also customizing the hardware to the workload has lot of untapped potential. RISC-V has a committee discussing accelerating dynamic languages for example. Memory tagging for automatic array bounds checking, pointer masking for helping GCs, custom instructions caches, etc. And you can go deeper; why not have a Node Webserver chip?
- bayindirh 3y ago> Large parts of the whole stack have been developed with trading off developer velocity vs performance. The time is always paid by someone. If developers decide to write the best code, they pay the price once in terms of development time. If the code is written with a developer velocity first perspective, every user pays the price every time they use the code. Also, developer velocity vs. program performance is not a correct perspective to look at it. I have used at least half a dozen libraries with great developer ergonomics and have world leading performance (e.g. Eigen, Catch2, easylogging++ from top of my head).
- transcriptase 3y agoAs far as I can tell hardware gains are enabling an entire generation of programmers to ignore the idea of taking optimization/performance into consideration entirely, outside of niche areas. The sluggishness, absurd loading times, and RAM usage for even the simplest applications on blisteringly fast hardware is astonishing.
- Rapzid 3y agoSeems fine to me.
- sylware 3y agoOnce we have a GPU filling the whole silicon real estate of a M2 chip, that with a 2nm process... I guess the next playstation? Even though I quite dislike the digital jail which are video game consoles, going to be hard to resist to FFXX.
- _hypx 3y agoThe problem with chiplets is that you can only fit so many of them in a realistic package. Once you hit that limit, you will need a way to pack more transistors on a single die. As a result, chiplets can only partial solve some of the issues of Moore's Law. It can't be a long-term extension of it.
- OliverGuy 3y agoI suppose that the packaging problem can be solved - up to a point - with stacking vertically as well as placing them next to the io die. Wonder how well that will scale, could we stack multiple chiplets high? What effect would that have on thermals?
- jackmott 3y ago[dead]
- _hypx 3y agoVertical chip stacking is another idea being proposed. But as you said, that will have thermal problems. It could be possible to stack less power-hungry chips like cache chips, but probably not the main CPU/GPU core. It will just be another way of extending Moore’s Law.
- bravetraveler 3y agoWould the X3D cache setup for the newer AMD CPUs count as vertical chips? I'm a bit naive of the actual... physical bits. I'm not clear what makes a chip, and if the cache would be that - or something a bit simpler
- jagger27 3y agoYes, it totally counts and is indeed being vertically stacked on Ryzen products today. Cache takes up a huge portion of total die area and doesn’t hurt temperatures too much. For now, AMD is using the technique to add more cache to their CPUs rather than moving all of it to another layer.
- anticensor 3y agoWirth's Law will eventually win.
- ilaksh 3y agoWhat about radical new compute-in-memory paradigms based on memristors or something? We really need more performance for running transformers. Not for general purpose CPUs.