> I don't know what you want. I don't want anything, I was correcting your misconceptions. > Well, if I go by "if it's part of the memory model then it's not

> I don't know what you want. I don't want anything, I was correcting your misconceptions. > Well, if I go by "if it's part of the memory model then it's not stale", then you can allow a relaxed ordering on single addresses without having stale data. I don't know what you're talking about. Memory ordering is not about ordering of a single address. That's cache coherency. [snip] > I'm pretty sure the entire point of acquire is that you can't reorder reads from after it to before it. And you're still wrong. Acquire barrier can be required even if you receive coherency updates in a sequential order. Barriers in modern processors do not flush, invalidate, or perform coherency operations. This is what I mean by you can't just handwave with a basic idea about the programming semantics (which aren't particularly complicated). It's easy to think up some vaguely plausible sounding implementation of those things, but the reality is infinitely more complicated. Real cache coherency protocols are verified with formal proofs, and not because they are easy. I guarantee if you handwave a new coherency state or give up some property of coherency, you will have bugs.