3 ms·
> Isn't it fair to characterize the cmos/fet switching losses as resistance to moving the charges around? Not really. It makes more sense to think about it as
by timerol 3y ago
> Isn't it fair to characterize the cmos/fet switching losses as resistance to moving the charges around?
Not really. It makes more sense to think about it as filling and emptying capacitors. You are charging the gate capacitance up to the supply voltage, then dumping that charge to discharge the gate to 0 again. The energy of each capacitance that gets charged and dumped is CV^2/2, which happens for each logic transition.
> I realize it we can't move charges around for free, but in some fantasy superconducting-fet logic circuit, wouldn't the power consumption be reduced?
If there was no resistance when distributing charge, it would help a bit, but not enough to change the clock frequency by more than 20%, assuming that the fantasy superconducting-fet had normal leakage and gate capacitance.
- saltcured 3y agoSo the charge is work and the discharge is waste? I guess I am entertaining the idea of an idealized Maxwell-demon CMOS circuit, if we could bounce the charge between gates with very little work to just pump the charge back and forth.
- timerol 3y agoThat's a reasonable way to think about it - you take energy from the supply voltage to charge the gate capacitor when the logic line goes high, then dump it when the logic line goes low. If you had a lossless bidirectional voltage converter circuit for each gate capacitance, then you could charge the capacitor from the supply and discharge it back into the supply, removing any switching losses.
- Dylan16807 3y agoThey're both waste. Charging a capacitor to 1 volt means your average input voltage is .5 and half your energy goes to heat. Discharging to a ground line wastes the other half. As the sibling comment says, you would need voltage converters running both ways to avoid this waste.