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Even when they are faster, the M2 is on the same die as the RAM and the bandwidth and latency are way better. That matters for compilation or am i mistaken?
by scns 3y ago
Even when they are faster, the M2 is on the same die as the RAM and the bandwidth and latency are way better. That matters for compilation or am i mistaken?
- jeffbee 3y agoYou are mistaken. Just like everyone else who has ever repeated the myth that Apple puts large-scale, high-performance logic and high density DRAM on the same die, which is impossible. Apple uses LPDDR4 modules soldered to a PCB, sourced from the same Korean company that everyone else uses. Intel has used the exact same architecture since Cannon Lake, in 2018.
- ricw 3y agoI don't think that is true. Last I checked apple M1 max chips have up to 800GB/s throughput, whilst AMDs high end chips taper out at around ~250GB/s or so, closer to what a standard M2 chip does (not max, or pro version). at the top end they've got at least 2x the memory bandwidth than other CPU vendors, and that's likely the case further down too.
- wmf 3y agoThe Mx Max should be compared to a discrete CPU+GPU combination that does have comparable total memory bandwidth. It isn't automatically better to put everything on one chip.
- jsheard 3y agoIt's worth noting that Apples stated bandwidth numbers aren't really attainable in CPU-only workloads, so for the sake of comparison to discrete CPUs they're not that useful. The M1 Max is advertised as having 400GB/sec bandwidth but the CPU cores can only use about half of that - still impressive, but not as impressive as you might think from the marketing. (The M1 Ultra is the one with 800GB/sec bandwidth on paper)
- inkyoto 3y agoAnandtech has measured the 104 Gb/sec per a CPU core for the M1 Max and 210 Gb/sec circa per a CPU cluster bandwidths. M1 Max has 3x CPU clusters: 1x power effecient (2x cores) and 2x performance ones (4x cores each). Where it gets interesting is how access to the memory is multiplexed in the most extreme case where 3x CPU clusters, 32x GPU and 16x ANE cores are attempting to fetch memory blocks at different locations and at once. It is not unreasonable to presuppose that Apple Silicon contraptions use the switched memory architecture, however with such a high degree of parallelism it is very intriguing to know how the memory architecture has been actually designed and optimised. High performant memory access has always been a big deal that usually comes with big money attached to it via a, naturally, non-memory bus associated connection.
- scns 3y agoThank you for the correction then. Ah yes the soldered LPDDR4 dies allow higher bandwiths since more pins allow parallel access.
- wtallis 3y agoCannon Lake is a weird red herring to bring in to the discussion, because it was only a real product in the narrowest sense possible. It may have technically been the first CPU Intel shipped with LPDDR4 support (or was it one of their Atom-based chips?), but the exact generation of LPDDR isn't really relevant because both Apple and Intel have supported multiple generations of LPDDR over the years and both have moved past 4 and 4x to 5 now. What is somewhat relevant as the source of confusion here is that Apple puts the DRAM on the same package as the processor rather than on the motherboard nearby like is almost always done for x86 systems that use LPDDR. (But there's at least one upcoming Intel system that's been announced as putting the processor and LPDDR on a shared module that is itself then soldered to the motherboard.) That packaging detail probably doesn't matter much for the entry-level Apple chips that use the same memory bus width as x86 processors, but may be more important for the high-end parts with GPU-like wide memory busses.
- jeffbee 3y agoLook, I had to go one way or the other: either I said it originated with Ice Lake mobile, and a pedant would come along and say Cannon Lake even though almost nobody physically possesses a Cannon Lake laptop, or I could say Cannon Lake, be pedantically correct, and get your response. Tiger Lake was probably even more widespread and that also predates Apple Silicon.
- wtallis 3y agoNone of those possibilities get you anywhere closer to being right. LPDDR didn't start with LPDDR4 so it doesn't matter which Intel processor was first to support LPDDR4. There's nothing special about that generation for Intel or Apple.
- inkyoto 3y agoFor the sake of the conversation, > Apple uses LPDDR4 modules soldered to a PCB, sourced from the same Korean company that everyone else uses. Apple might have sourced and soldered on LPDDR modules from the same company, but it is not LPDDR4 and it is LPDDR5 6400 connected via a 256 (Pro), 512 (Max) or 1024 (Ultra) bit wide memory bus. > Intel has used the exact same architecture since Cannon Lake, in 2018. Other than LPDDR5 6400 had not existed in 2018, no Intel CPU has ever used a 512, leave alone 1024, bit wide memory bus even in the server setup. Wide memory bus is conducive of faster concurrent complex builds, and Rust / Haskell builds show significantly faster build speeds as well.
- kiratp 3y agoCase in point > Rust, cargo build for our "test world binary".: 64 core Threadripper 3990x @ PBO level 3, ~400w, with Optane drive - 1 min 37s M1 Max, 64 GB, on battery @ 30% charge - 1:34s https://twitter.com/kiratpandya/status/1457438725680480257 https://twitter.com/kiratpandya/status/1457438725680480257
- MBCook 3y agoIt’s not on die, but isn’t it on package? Thus making signal lengths much shorter and allowing more lines making the memory bandwidth much higher than a (theoretical) equivalent chip with the memory soldered to the motherboard like the Intel machines were?
- kcb 3y agoYea theoretically, but in memory latency tests the M series chips are well behind Intel and AMD systems.