11 ms·

How Does an FPGA Work?

313 points by sph 4y ago

nuancebydefault 4y ago
It seems that operations on FPGAs can run much more efficiently than their cpu equivalent. For an 'AND' operation, a cpu needs to load code and data from a memory into registers, run the logic and write the result register back to some memory. This while filling up the pipeline for subsequent operations. The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? I could ask GPT those questions, but the HN community will provide more insight I guess.
- JackSlateur 4y ago
  For the same reasons we do not replace CPUs with GPUs: not the right tool Check out the instruction set of modern CPUs
- burnished 4y ago
  They both use the same kind of components; the FPGA does not have a speed advantage, you are simply comparing the speed of a very simple circuit element to the speed of a very complicated pipeline. You would use an FPGA to simulate a special purpose circuit, which would be faster than a CPU for its specific purpose. We have CPUs because having a general purpose processing chip is incredibly handy when you want to be able to do more than one thing. EDIT: I forgot to mention that the device outputs in one clock cycle by definition: if your clock is too fast then your components output signals dont have time to stabilize and you will get read errors, so you ensure your clock is slow enough for everything to stabilize.
- convolvatron 4y ago
  one big problem is memory. basic cpus have alot of facilities for high-speed synchronous interface with DRAM, and truly vast amount of resource for cache. partially as a result, a good model for compiling code to fpgas uses a dataflow paradigm, since we don't need to serialize all operations through a memory fetch, cache, or even register file. if we hadn't decided to move all our computing to the cloud, I suspect fpga accelerator boards for applications which map well to that model would have some traction in specialized areas. signal processing is definitely one such.
- quadrature 4y ago
  >One might ask, why are cpus not being replaced by FPGAs? they do sometimes !, for very specific applications. The problem is that an FPGA is programmed for one specific task and would have to be taken offline and reprogrammed if you wanted to do something else with it. Its not general purpose like a CPU where you can load up any program and have it run. Programming an FPGA is also comparatively much harder to reason about than a CPU because of the parallelism and timing you described.
  - MSFT_Edging 4y ago
    Some of the more modern Xilinx stuff has features where you don't need to take down the whole FPGA to reload a bitstream onto part of the chip. Its really neat, you can do live reprogramming of one component and leave the others alone or have an A/B setup where one updates while the other is unchanged.
    - JohnFen 4y ago
      Yes, I'm working on a Xilinx ARM processor with an FPGA. The FPGA and the CPU are independent units in the chip that can each operate with or without the other. We can indeed reprogram the FPGA without taking the system down.
      - davemp 4y ago
        It goes even further. You can partially reconfigure the FPGA fabric itself: https://support.xilinx.com/s/article/34924?language=en_US https://support.xilinx.com/s/article/34924?language=en_US
        MSFT_Edging 4y ago
        That's what I was referring to. Neat stuff.
    - quadrature 4y ago
      That is really cool, hadn't heard of that before.
- barelyauser 4y ago
  What is simpler: making logical circuit "A" or making a circuit that emulates logical circuit "A" and its relatives?
- Lramseyer 4y ago
  These are really good questions to be asking, and to help with that let's consider 3 attributes of compute complexity: time, space, and memory The traditional way of computing on a CPU is in essence a list of instructions to be computed. These instructions all go to the same place (the CPU core) to be computed. Since the space is constant, the instructions are computed sequentially in time. Most programmers aren't concerned with redesigning a CPU, so we typically only think about computing in time (and memory of course) On an FPGA (and custom silicon) the speedup comes from being able to compute in both time and space. Instead of your instructions existing in memory, and computed in time, they can be represented in separate logic elements (in space) and they can each do separate things in time. So in a way, you're trading space for time. This is how the speed gains are achieved. Where this all breaks down is the optimization and scheduling. A sequential task is relatively easy to optimize since you're optimizing in time (and memory to an extent.) Scheduling is easy too, since, they can be prioritized and queued up. However, when you're computing in space, you have to optimize in 2 spatial dimensions and in time. When you have multiple tasks that that need to be completed, you then need to place them together and not have them overlap. Think trying to fit a ton of different shaped tiles on a table, where you need to be constantly adding and removing tiles in a way that doesn't disrupt the placement of other tiles (at least not too often.) It's kind of a pain, but for some more constrained problem sets, it might make sense. These aren't impossible problems, and for some tasks, the time or power usage savings is worth the additional complexity. But sequential optimization is way easier, and good enough for most tasks. However, if our desire for faster computing outpaces our ability to make faster CPUs, you may see more FPGAs doing this sort of thing. We already have FPGAs that are capable of partial reconfiguration, and some pretty good software tools to go along with it. TL;DR: Geometry is hard.
- toast0 4y ago
  > The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? FPGAs are more or less a flexible replacement for an application specific (logic level) integrated circuit. A CPU can do a wide variety of tasks, with a small penalty for switching tasks. An ASIC can do one thing and that's it, a FPGA can do many things, but with a large penalty for task switching. (you can have a CPU as an ASIC or an FPGA, but...). ASICs require a lot of upfront design work and costs, so you can't use them for everything. ASICs and especially CPUs tend to be able to achieve a higher clock speed that FPGAs, but it kind of depends. > Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? Not really; the way problems are solved is drastically different, and I'd expect most things would need to be reconceptualized to fit. And a lot of software isn't really suited to living as a logic circuit. Exceptions would be encoding, compression, encryption, the inverses of all of those, signal processing, etc. Things where you have a data pipeline and 'the same thing' happens to all the data.
- jcranmer 4y ago
  FPGAs are the next big frontier for software development, and have been since the '90s, they just need the programming model worked out. This is the traditional story told about FPGAs, but GPGPU programming suddenly overtaking FPGA development about 2010 despite their awkward programming models makes that story rather suspect. The thing is, a lot of the benefits of FPGAs are really best-case scenarios, and when you move to more typical scenarios, their competitiveness as an architecture dwindles dramatically. Pipelining on an FPGA requires being able to find, and fill, spatial duplication of the operations being done. If you've got conditional operations in a pipeline, now your pipeline isn't so full anymore, and this hurts performance on an FPGA far more than on a CPU (which spends a lot of power trying to keep its pipelines full). But needing to keep the pipelines spatially connected also means you have to be able to find a physical connection between the two stages of a pipeline, and the physical length of that connection also imposes limitations on the frequency you can run the FPGA at. If you care about FLOPS (or throughput in general), the problem with FPGAs is that they are running at a clock speed about a tenth of a CPU. This requires a 10x improvement in performance just to stand still; given that software development for FPGAs requires essentially a completely different mindset than for CPUs or even GPUs, it's not common to have use cases that work well on FPGAs. (I should say that a lot of my information about programming FPGAs comes from ex-FPGA developers, and the "ex-" part will certainly have its own form of bias in these opinions).
  - davemp 4y ago
    Yeah I don't really see FPGAs ever making their way down to consumers the way GPUs and CPUs have (end users actually programming them). For (semi) fixed pipeline operations FPGAs will basically always be worse than some slightly more specialized ASIC like a GPU/AI engine. One area FPGAs can be exceptionally good at is real-time operations. You have much better control over timing in the general on FPGAs vs MCU/CPUs, but I don't think that's inherent (you could probably alter the mcu architecture a bit and close the gap). I could be wrong but I also think you get better power draw for things like mid to low volume glue chips in embedded systems because you're not powering big SRAM banks and DMAs just to pipe data between a couple hardware interfaces. This is only because of market forces though obviously, because if mid to low volume ASICs become viable in terms of dev time they'll be much better.
- pjc50 4y ago
  > One might ask, why are cpus not being replaced by FPGAs? Most of the time you want data-dependent execution. FPGA systems excel at "fixed pipeline" systems, where you have e.g. an audio filter chain .. but even that is usually done in efficient DSP CPUs. > Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? A subset can. Things like recursion are right out. Various companies have tools to do this, but you usually end up having to rework either the source you're feeding them, or the HDL output.
- pfyra 4y ago
  > Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? Yes. At least for c and c++. It is called High Level Synthesis.
- rcxdude 4y ago
  The very lowest-level operations on FPGAs can run more efficiently than emulating them on an CPU. The higher level operations, which is usually what we want, are slower, as a 'gate' in an FPGA is approximately an order of magnitude slower, more power hungry, and expensive than a gate in a CPU (or GPU). modern CPUs excel at executing data-dependent operations of a wide variety while exploiting as much parallelism as available, while GPUs excel at churning through a huge amount of memory doing parallel arithmetic operations: for both of theses tasks an FPGA is going to be worse. For an FPGA to be the better option you need a task which is specialised enough that the speedup from designing a specialised circuit to do it overcomes the intrinsic slowdown from it being implemented in an FPGA as opposed to raw silicon, and these are not your typical software tasks, usually much more hardware-type tasks. The two areas where FPGAs excel are having extremely low and predictable latency, and having lots of extremely flexible high-bandwidth IO (still less bandwidth than the memory or PCI-E bandwidth of a GPU, but it's close and it's much more flexible). For computation throughput, however, there's only a few niche applications, though one important one is simulating the logic which is going to be implemented in a CPU, GPU, or ASIC to validate it before the expensive process of actually etching some silicon.
- cpgxiii 4y ago
  > The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? You need to be careful with interpreting cycle counts as execution time. A naive operation on an FPGA may take a single cycle because the author has asked for that, rather than constructing and using a pipelined multi-cycle ALU [1]. Therefore the design tool will synthesize a layout that performs the operation in a single cycle, but the cycle time (and thus clock frequency for that portion of the layout) will be limited by however long that operation needs to complete, and will be much longer than the cycle time of the CPU you are comparing against. Note that a CPU almost certainly has "better" ALUs than those you'd get on an FPGA - optimized fixed-function circuits can always be faster than their generic programmable equivalents - the advantage of the FPGA is that you can have only (and more of) the operations you need, running in parallel as many times as the device will support. You could make a CPU by which every instruction (even very complicated vector instructions like AVX or SVE) was completed entirely in a single cycle, but that cycle itself would be very long, and all of the incredible throughput benefits of pipelined execution would be lost. [1] Pretty much all of the vendor design tools can instantiate an ALU for your device, given parameters like # of bits, operation types, # of cycles, etc.
burnished 4y ago
Neat. If the author is around, might I suggest pushing some of the 'why use an FPGA' to the front? I think it would benefit from a more concrete example motivating the use of an FPGA - like a picture of some simple circuit using a seven segment display on a broad board next to a picture of an FPGA implementing the same circuit in order to make it more clear that it is a substitute for putting experiments together by hand. I think it will help newcomers better contextualize what is happening and why. I think in the same vein your wrap up of why you might want to do something in hardware vs software is great and well placed. Hmmm, I guess now is as good a time as any to bumblefuck around with small electronics projects for fun. Thanks for the reminder!
- beardyw 4y ago
  > Neat. If the author is around, might I suggest pushing some of the 'why use an FPGA' to the front? I think the problem is identifying cases where you really need an FPGA. Most of the time you don't.
  - asdfman123 4y ago
    This is meant to be an introduction though, right? You can simply write “some people do X, and others claim Y is better” then move on. I read several paragraphs of the article and I still don’t know why you’d use one, despite taking computer architecture and analog electronics courses in undergrad. I don’t want to read about logic gates again and I don’t want to read about the nuances before I broadly understand what the point is. For anyone else still wondering, here’s Wikipedia: > FPGAs have a remarkable role in embedded system development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture. Basically, rapid prototyping I guess. That makes sense.
    - awjlogan 4y ago
      If that was an ask for a specific example, one of the most common uses for FPGAs is DSPs. Say you have a simple FIR filter of, say, 63 taps. To do this in a CPU requires you to load two values and do a multiply/accumulate for each tap in sequence. Very (!!) optimistically, that’s about 192 instructions. With an FPGA, you can do all the multiplications in parallel and then just sum the outputs - probably done in 2 cycles and with pipelining your throughput could be a sample every clock. If the FPGA is too slow, too power inefficient etc you can (if you have the money!) take the same core design and put it in an ASIC. The FPGA provides an excellent prototyping environment; in this example you can tune the filter parameters before committing to a full ASIC.
jschveibinz 4y ago
We used them for real time array signal processing and beam-forming. They worked great.
- brooksbp 4y ago
  super wide AXI-Stream busses?
sph 4y ago
Sadly the article doesn't go into details about how the programmable RAM is wired to the actual logic gates, which seems to me the most interesting and challenging part of designing an FPGA. In my mediocre understanding of digital circuits, RAM is usually addressable, so it has to be wired in a more direct manner to enable such a design. I posted this article because someone mentioned some Ryzen chip having an FPGA in another post, and I am now left wondering: 1. why don't we have more user-programmable FPGAs in our fancy desktop mainboards 2. is there a SoC board, ARM or RISC-V based, with an FPGA on board? The slower the CPU, the more useful an FPGA would be to accelerate compute tasks
- MSFT_Edging 4y ago
  As for question 1, they're far more common in server grade stuff where typically they are baked in. Consumer stuff just doesn't need/use as much IO throughput and muxing that the FPGA provides on say, a large networking switch. There are PCIe compatible FPGAs that you can plug into your desktop like a graphics card to accelerate certain tasks. In general though, our workstation hardware just isn't specialized enough to require them, but can be extended to do so. If something is a large enough business model, they'll just make an ASIC.
- rjsw 4y ago
  There are plenty of boards that have one of the combined ARM & FPGA chips, Zynq (Xylinx/AMD) or Cyclone (Altera/Intel).
- duskwuff 4y ago
  > Sadly the article doesn't go into details about how the programmable RAM is wired to the actual logic gates Not sure what you mean by that. Do you mean how a RAM is used as a lookup table to implement logic gates, how routing works, or how block RAM is integrated into the FPGA fabric? > is there a SoC board, ARM or RISC-V based, with an FPGA on board? Better yet, there are a number of FPGAs available with an ARM SoC on board. Xilinx Zynq, Intel Cyclone V SoC, various others.
- wildzzz 4y ago
  Both Intel and Xilinx sell FPGAs with hard ARM cores inside so you can run real Linux while being able to interface with custom logic. Additionally, it's pretty common to create ARM, RISC-V, or PowerPC soft cores in the FPGA when there is no hard cores available. These mimic the real cores and will run software while allowing for things like custom instructions that can take advantage of the flexibility of FPGA fabric. The Xilinx Zynq and Intel Cyclone V have options for hard ARM cores. There are various designs of boards out there you can buy that implement Arduino or Raspberry Pi shield compatibility. The XUP PYNQ-Z2 supports both interfaces and runs a Zynq-7000 with a real ARM core. You can do other things with soft cores that are not possible with an off the shelf CPU like triple mode redundancy. This is when you run a lot of the logic in triplicate and vote on the results to prevent a bit flip from messing up the software. This is common for space-based CPUs that are running on FPGAs. It's expensive to design a new chip in a very small run so it's much cheaper to just put the core on an off the shelf FPGA and use the rest of the FPGA fabric for custom logic functions.
markx2 4y ago
If anyone in unaware you can buy the very impressive Pocket. https://www.analogue.co/pocket https://www.analogue.co/pocket The current list of what it can do with FPGA is listed here - https://openfpga-cores-inventory.github.io/analogue-pocket/ https://openfpga-cores-inventory.github.io/analogue-pocket/ and the inevitable sub-reddit is a good resource. https://old.reddit.com/r/AnaloguePocket/ https://old.reddit.com/r/AnaloguePocket/
- jonny_eh 4y ago
  I also recommend the official dock. It basically turns it into an easy to use Mister.
- gchadwick 4y ago
  There's also the MiSTer project: https://github.com/MiSTer-devel/Wiki_MiSTer/wiki https://github.com/MiSTer-devel/Wiki_MiSTer/wiki. Not hand-held (yet...) and hardware is less slick but a bunch more systems and also fully open source.
  - phendrenad2 4y ago
    MiSTer makes me kind of sad, the DE10-nano board it's based on is 7 years old at this point, and the actual FPGA chip on the board is probably over twice as old as that. And this is still the peak of hobby FPGA chips. I wonder why Moore's Law is hitting the FPGA industry particularly hard all of a sudden.
    - willis936 4y ago
      There are better FPGA options, they're just more expensive. The DE-10 Nano was strategically chosen as "powerful enough to meet most wants while still being within a reasonable budget". No one's going to plunk down $10k for a 19 EV Zynq UltraScale+ with 1.1M LEs, but they will spend $200 on a Cylcone V with 210k LEs.
      - fooblaster 4y ago
dddiaz1 4y ago
Another really cool use case for FPGAs is for ultra fast analysis of genomic data. This guide walks you through setting up an F1 instance (AWS FPGA) to do that: https://aws-quickstart.github.io/quickstart-illumina-dragen/ https://aws-quickstart.github.io/quickstart-illumina-dragen/
nfriedly 4y ago
I've read that AMD's 7040-series mobile CPUs will have an "FPGA-based AI engine developed by Xilinx" [1] - I'm wondering how programmable that will be. I know there's been some performance difficulties emulating the PlayStation 3's various floating point modes. It's the kid of thing that I think an on-chip FPGA could theoretically help with, although I don't know if it'd be worth the trouble in this specific case. (Or if AMD's implementation will be flexible enough to help.) [1]: https://www.anandtech.com/show/18844/amd-unveils-ryzen-mobile-7040u-series-phoenix-to-fly-into-thin-notebooks https://www.anandtech.com/show/18844/amd-unveils-ryzen-mobil...
photochemsyn 4y ago
Here's a nice series that picks up where this one leaves off (shows how flip-flop/LUT units are organized into cells inside a PLB, programmable logic block). It also is the first step in a tutorial on using Verilog, building a hardware finite state machine, and eventually a RISC-V processor on a FPGA: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-1-what-is-an-fpga/3ee5f6c8fa594161a655a9f960060893 https://www.digikey.com/en/maker/projects/introduction-to-fp...
user070223 4y ago
From my understanding FPGA doesn't have the instruction pipeline as the command is encoded in the gates themselves. It means that on runtime the FPGA is not turing complete[0] as opposed to the CPU[1]. There is a phrase "data is code and code is data" in security context. The new saying if FPGA would ever replace cpus' as the main computation hardware(as you don't need turing complete when you keep using the same apps[microservices]) is something like "code is execution and execution is code" as you imprint the code in the gates. It would get rid of a whole class/subclass of memory safety vulernabilitie. This paradigm change is like what webassembly did to the web. The slogan should be "make the bitstream go mainstream" Some made a demo running wasm on fpga[1], not sure if using a cpu or directly of course you move complexity to compiling, and increase loading speed, all for order of magnitude faster execution Companies devloped high level synthesis compilers but it's diffcult and challenging as you need to synchronize parallel excution piplines which you don't have to in cpu since it has steady clock rate for each step in the pipeline A copmany named legup computing(acquired by microchip) compiled memcached/redis applications to fpga and improved perfromance & power efficency by an order of magnitude(10x) There are a lot of intellectual properties in hardware design as opposed to software so tools and knowledge is scarce. If anyone works / want to work on this problem hit me up in the comments [0] Unless you implement a cpu on top of the fpga :) [1] Assuming infinte memory, which is false, but good enough [2] https://github.com/denisvasilik/wasm-fpga https://github.com/denisvasilik/wasm-fpga
- proto_lambda 4y ago
  > FPGA doesn't have the instruction pipeline as the command is encoded in the gates themselves. It means that on runtime the FPGA is not turing complete[0] as opposed to the CPU[1]. That obviously depends entirely on the circuit, many sufficiently advanced circuits probably end up being accidentally turing complete.
  - JohnFen 4y ago
    You can implement turing-complete CPUs in FPGA fabric.
    - 4y ago
mpd 4y ago
I really enjoyed the recent Hackerbox[0] featuring an FPGA. I'd never worked with one prior to that. https://hackerboxes.com/collections/past-hackerboxes/products/hackerbox-0088-fpga-lab https://hackerboxes.com/collections/past-hackerboxes/product...
jokoon 4y ago
So can a large FPGA be somehow used to brute force encryption? I don't really understand electronics to see if a GPU could be faster than a FPGA, but my guess is yes? It seems that anything that can be programmed is inherently slower than a FPGA equivalent doing the same task. Does larger enough key size always defeat a FPGA? I would guess that it becomes power and cost prohibitive for a private company to deliver such possibility, but of course, a large government entity like the NSA might have enough resource to pay for enough FPGA to decrypt most things.
- braho 4y ago
  Even though the FPGA fabric might encode the solution more effectively, there are other important differentiators: clock speed and memory bandwidth. GPUs have higher clock speeds and typically better memory bandwidth (related of course). With the higher clock speed, GPUs can well outperform FPGAs for many problems.
- dreamcompiler 4y ago
  > So can a large FPGA be somehow used to brute force encryption? Yes and no. It is usually possible to use an FPGA to build a specific logic circuit that will run some particular algorithm faster than the algorithm would run on a general-purpose CPU. (By a factor of maybe 2x to 100x. It varies a lot depending on the algorithm.) It is also the case that if you implement that algorithm on a dedicated custom chip it can always be designed to run faster than the equivalent FPGA. So if you really want maximum speed, spend the megabucks for dedicated silicon. That said, modern GPUs and DSP chips might be able to run some algorithms almost as fast as dedicated silicon and faster than FPGAs. So maybe you don't need megabucks. Again, it depends on the algorithm. In any case you'd need many orders of magnitude of speedup to usefully brute-force a modern crypto algorithm, and the most you'd get even from dedicated silicon is about three. Useful speedup requires quantum computers -- which don't yet exist -- and even quantum computers will only help break asymmetric crypto, not symmetric crypto.
  - jokoon 4y ago
    for AES, for example?
y0ungarmanii 4y ago
I saw various comments about how FPGAs are not ready for consumer hardware, apple is using them in the airpod max already (probably for filtering audio) Check the link below https://www.ifixit.com/Teardown/AirPods+Max+Teardown/139369 https://www.ifixit.com/Teardown/AirPods+Max+Teardown/139369 They really excel for high throughput & low latency - which noise canceling sounds like a good example of! In addition to this, they are already being used in communication systems & data centers to speed up latency sensitive computations. Edge AI seems like a big market that they will be used for soon, probably more likely b/c they can be flashed unlike ASICs and new NN architectures drop every couple of years.
- kimburgess 4y ago
  There’ll also extremely common in most hardware used for any realtime media processing. With them being mutable it can be updated to support new compression methods, or switched in field to drop a device between acting as an encoder or decoder.
pwpw 4y ago
The MiSTer project[0] is a wonderful open-source introduction to a practical use case for FPGAs. It uses verilog to describe how the DE10-Nano chip should be set up to resemble various classic computers, arcade machines, and video game consoles. With a single device you can have an Apple II+, Super Street Fighter II Turbo, and a SNES. Currently it supports up to the PlayStation for console cores, which is probably the upper bounds for the DE10-Nano. If you want more info, My Life in Gaming has a great overview video[1] of the MiSTer that covers it in depth. The entire project feels perfectly in line with hacker mentality and is exciting to watch grow. There's nothing like playing Super Metroid with an original SNES controller on a CRT at the end of the day. [0] https://github.com/MiSTer-devel/Wiki_MiSTer/wiki https://github.com/MiSTer-devel/Wiki_MiSTer/wiki [1] https://www.youtube.com/watch?v=rhT6YYRH1EI https://www.youtube.com/watch?v=rhT6YYRH1EI
- idonotknowwhy 4y ago
  Or Time Crisis, with the original light guns on a CRT
deleted 4y ago
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qiqitori 4y ago
If anyone's interested in getting into FPGA stuff, the iCE40UP5K (the 5K indicates the number of LUTs; there are other sizes available) has an open-source toolchain that works very well. There are pretty cheap development boards using this FPGA, I use the UPduino, which I bought in 2019 or so. (Recently the same team released a new UPduino dev board that also includes an RP2040, which is probably pretty useful, available at https://lectronz.com/products/pico-ice-rp2040-plus-lattice-ice40up5k-fpga https://lectronz.com/products/pico-ice-rp2040-plus-lattice-i...) What can you do with an FPGA of this size? Not too much, but it's about enough to, for example, fit an implementation of a YM2151 FM audio chip (audio chip from the 80s that was used in synthesizers and arcade machines). I think it would probably also be big enough for old CPUs such as the Z80 or 6502. Unfortunately it's not 5V-tolerant so you can't wire it directly to parts of that era.
- yummypaint 4y ago
  I second the upduino, it's a great board. Recently i have been using the iCESugar-pro which is also supported by the open source toolchain, and comes in a handy SODIMM form factor that makes it easy to incorporate into real projects. It uses the lattice LFE5U-25F-6BG256C with 24k LUTs and 32 MB SDRAM, 106 usable i/o connections, about $60.
cubefox 4y ago
It seems FPGAs are universal Turing machines (in contrast to ASICs, which are not generally universal), which would make them similar to CPUs. But CPUs are clearly "more universal" in some sense. Perhaps because CPUs can change their programs at run time, which doesn't seem possible for FPGAs. Unfortunately the article doesn't compare FPGAs to CPUs.
- agg23 4y ago
  That's actually one of the coolest parts about FPGAs. Partial Reconfiguration (Intel docs for example) - https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/partial-reconfiguration.html https://www.intel.com/content/www/us/en/software/programmabl... It's expensive, but it can be very useful.
blopp99 4y ago
I don't know if I'm online on this one but the only thing that have stoped me from finally learning FPGA it's a practical use for me or my Profesional life. I have not yet encounter a situation besides the bucket list item of making a chip, which btw I don't even need to know FPGA at this point to complete this, that has made me seriously sit and Lear FPGA
bschwindHN 4y ago
Is there a good "starter" FPGA kit which has an open-source toolchain, and the ability to build/deploy everything from the command line? I'm going through links in the comments here now in search of this too. It would be cool to hook up an FPGA to an image sensor and do my own processing from the raw sensor data. Based on that description, I'm not sure which dev board or starter kit would be best to be looking at.
- xkriva11 4y ago
  look for example at iCESugar-nano, low spec but fits your requirements https://github.com/wuxx/icesugar-nano https://github.com/wuxx/icesugar-nano
  - bschwindHN 4y ago
    Oh this looks perfect, thanks! Here's one more thing I don't know - how do you evaluate whether or not an FPGA is sufficient for what you want to do? For example, let's say I want to talk to an image sensor which has a 3088x2076 resolution, and either capture still images or maybe video at some frame rate. Which specs do I need to hone in on and evaluate to determine which FPGAs would work, and which won't?
JohnMakin 4y ago
these are much cheaper to produce and run, not to mention more flexible than GPU’s for LLM training. as an added benefit you can write (if you were so inclined) hardware-level logic to whatever workload you want. reprogrammable as well. -background : 4-5 years ago worked on embedded systems tech that used these for fintech. they seemed like the future back then and LLM workloads were barely a thing. Glad more people are learning about them.
djmips 4y ago
People should make their software faster before they turn to FPGAs. Unless you already did that! But FPGA is a lot of fun to learn and play with even if you don't have a ready application.
- yummypaint 4y ago
  On the other hand, there are fpga boards priced comparably to microcontrollers now. It can be very refreshing and useful to escape the "programming" paradigm. Hobbyists are already contributing the value of their time which is generally much larger than the cost difference between device types, so in a sense the fpga barrier to entry may actually be higher for companies than individuals at the moment.
kepler1 4y ago
Although it was a little bit of a long way to get to a point, I did somewhat appreciate the article's going into the idea of the circuit structure and look up tables. It made me think (and I don't know if this is an apt analogy), it's like if you have 2 versions of a machine responsible for sorting different size balls in a factory. One of them (#1) is built with pipes that exactly encode (in hardware, like a grid of holes) which balls are allowed to pass which size buckets on a production line. The other (#2) uses a robot that looks at each ball passing by, does some measurements, and decides whether it's the right size for a certain bucket. (#1) is not very flexible, but is really great at the job and can do it just by shaking the tray and works for thousands of balls at once. (#2) needs to take time to study each one passing by. But you can reprogram it more easily. Each has its purpose. And the FPGA tries to give you the advantages of #1 with a bit more flexibility to change the size of the holes, etc. Then, replace balls with input video files that need an efficient decoder in hardware, etc. and I see the link.
Eumenes 4y ago
Great overview. I do wonder if FPGAs will make a run against modern server/GPU cluster setups for AI/ML.

313 points by sph 4y ago

It seems that operations on FPGAs can run much more efficiently than their cpu equivalent. For an 'AND' operation, a cpu needs to load code and data from a memory into registers, run the logic and write the result register back to some memory. This while filling up the pipeline for subsequent operations. The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? I could ask GPT those questions, but the HN community will provide more insight I guess.

JackSlateur 4y ago
For the same reasons we do not replace CPUs with GPUs: not the right tool Check out the instruction set of modern CPUs
burnished 4y ago
They both use the same kind of components; the FPGA does not have a speed advantage, you are simply comparing the speed of a very simple circuit element to the speed of a very complicated pipeline. You would use an FPGA to simulate a special purpose circuit, which would be faster than a CPU for its specific purpose. We have CPUs because having a general purpose processing chip is incredibly handy when you want to be able to do more than one thing. EDIT: I forgot to mention that the device outputs in one clock cycle by definition: if your clock is too fast then your components output signals dont have time to stabilize and you will get read errors, so you ensure your clock is slow enough for everything to stabilize.
convolvatron 4y ago
one big problem is memory. basic cpus have alot of facilities for high-speed synchronous interface with DRAM, and truly vast amount of resource for cache. partially as a result, a good model for compiling code to fpgas uses a dataflow paradigm, since we don't need to serialize all operations through a memory fetch, cache, or even register file. if we hadn't decided to move all our computing to the cloud, I suspect fpga accelerator boards for applications which map well to that model would have some traction in specialized areas. signal processing is definitely one such.
quadrature 4y ago
>One might ask, why are cpus not being replaced by FPGAs? they do sometimes !, for very specific applications. The problem is that an FPGA is programmed for one specific task and would have to be taken offline and reprogrammed if you wanted to do something else with it. Its not general purpose like a CPU where you can load up any program and have it run. Programming an FPGA is also comparatively much harder to reason about than a CPU because of the parallelism and timing you described.
- MSFT_Edging 4y ago
  Some of the more modern Xilinx stuff has features where you don't need to take down the whole FPGA to reload a bitstream onto part of the chip. Its really neat, you can do live reprogramming of one component and leave the others alone or have an A/B setup where one updates while the other is unchanged.
  - JohnFen 4y ago
    Yes, I'm working on a Xilinx ARM processor with an FPGA. The FPGA and the CPU are independent units in the chip that can each operate with or without the other. We can indeed reprogram the FPGA without taking the system down.
    - davemp 4y ago
      It goes even further. You can partially reconfigure the FPGA fabric itself: https://support.xilinx.com/s/article/34924?language=en_US https://support.xilinx.com/s/article/34924?language=en_US
      - MSFT_Edging 4y ago
        That's what I was referring to. Neat stuff.
  - quadrature 4y ago
    That is really cool, hadn't heard of that before.
barelyauser 4y ago
What is simpler: making logical circuit "A" or making a circuit that emulates logical circuit "A" and its relatives?
Lramseyer 4y ago
These are really good questions to be asking, and to help with that let's consider 3 attributes of compute complexity: time, space, and memory The traditional way of computing on a CPU is in essence a list of instructions to be computed. These instructions all go to the same place (the CPU core) to be computed. Since the space is constant, the instructions are computed sequentially in time. Most programmers aren't concerned with redesigning a CPU, so we typically only think about computing in time (and memory of course) On an FPGA (and custom silicon) the speedup comes from being able to compute in both time and space. Instead of your instructions existing in memory, and computed in time, they can be represented in separate logic elements (in space) and they can each do separate things in time. So in a way, you're trading space for time. This is how the speed gains are achieved. Where this all breaks down is the optimization and scheduling. A sequential task is relatively easy to optimize since you're optimizing in time (and memory to an extent.) Scheduling is easy too, since, they can be prioritized and queued up. However, when you're computing in space, you have to optimize in 2 spatial dimensions and in time. When you have multiple tasks that that need to be completed, you then need to place them together and not have them overlap. Think trying to fit a ton of different shaped tiles on a table, where you need to be constantly adding and removing tiles in a way that doesn't disrupt the placement of other tiles (at least not too often.) It's kind of a pain, but for some more constrained problem sets, it might make sense. These aren't impossible problems, and for some tasks, the time or power usage savings is worth the additional complexity. But sequential optimization is way easier, and good enough for most tasks. However, if our desire for faster computing outpaces our ability to make faster CPUs, you may see more FPGAs doing this sort of thing. We already have FPGAs that are capable of partial reconfiguration, and some pretty good software tools to go along with it. TL;DR: Geometry is hard.
toast0 4y ago
> The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? FPGAs are more or less a flexible replacement for an application specific (logic level) integrated circuit. A CPU can do a wide variety of tasks, with a small penalty for switching tasks. An ASIC can do one thing and that's it, a FPGA can do many things, but with a large penalty for task switching. (you can have a CPU as an ASIC or an FPGA, but...). ASICs require a lot of upfront design work and costs, so you can't use them for everything. ASICs and especially CPUs tend to be able to achieve a higher clock speed that FPGAs, but it kind of depends. > Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? Not really; the way problems are solved is drastically different, and I'd expect most things would need to be reconceptualized to fit. And a lot of software isn't really suited to living as a logic circuit. Exceptions would be encoding, compression, encryption, the inverses of all of those, signal processing, etc. Things where you have a data pipeline and 'the same thing' happens to all the data.
jcranmer 4y ago
FPGAs are the next big frontier for software development, and have been since the '90s, they just need the programming model worked out. This is the traditional story told about FPGAs, but GPGPU programming suddenly overtaking FPGA development about 2010 despite their awkward programming models makes that story rather suspect. The thing is, a lot of the benefits of FPGAs are really best-case scenarios, and when you move to more typical scenarios, their competitiveness as an architecture dwindles dramatically. Pipelining on an FPGA requires being able to find, and fill, spatial duplication of the operations being done. If you've got conditional operations in a pipeline, now your pipeline isn't so full anymore, and this hurts performance on an FPGA far more than on a CPU (which spends a lot of power trying to keep its pipelines full). But needing to keep the pipelines spatially connected also means you have to be able to find a physical connection between the two stages of a pipeline, and the physical length of that connection also imposes limitations on the frequency you can run the FPGA at. If you care about FLOPS (or throughput in general), the problem with FPGAs is that they are running at a clock speed about a tenth of a CPU. This requires a 10x improvement in performance just to stand still; given that software development for FPGAs requires essentially a completely different mindset than for CPUs or even GPUs, it's not common to have use cases that work well on FPGAs. (I should say that a lot of my information about programming FPGAs comes from ex-FPGA developers, and the "ex-" part will certainly have its own form of bias in these opinions).
- davemp 4y ago
  Yeah I don't really see FPGAs ever making their way down to consumers the way GPUs and CPUs have (end users actually programming them). For (semi) fixed pipeline operations FPGAs will basically always be worse than some slightly more specialized ASIC like a GPU/AI engine. One area FPGAs can be exceptionally good at is real-time operations. You have much better control over timing in the general on FPGAs vs MCU/CPUs, but I don't think that's inherent (you could probably alter the mcu architecture a bit and close the gap). I could be wrong but I also think you get better power draw for things like mid to low volume glue chips in embedded systems because you're not powering big SRAM banks and DMAs just to pipe data between a couple hardware interfaces. This is only because of market forces though obviously, because if mid to low volume ASICs become viable in terms of dev time they'll be much better.
pjc50 4y ago
> One might ask, why are cpus not being replaced by FPGAs? Most of the time you want data-dependent execution. FPGA systems excel at "fixed pipeline" systems, where you have e.g. an audio filter chain .. but even that is usually done in efficient DSP CPUs. > Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? A subset can. Things like recursion are right out. Various companies have tools to do this, but you usually end up having to rework either the source you're feeding them, or the HDL output.
pfyra 4y ago
> Another interesting question, can software (recipes for cpus) be transpiled to be efficiently run on FPGAs? Yes. At least for c and c++. It is called High Level Synthesis.
rcxdude 4y ago
The very lowest-level operations on FPGAs can run more efficiently than emulating them on an CPU. The higher level operations, which is usually what we want, are slower, as a 'gate' in an FPGA is approximately an order of magnitude slower, more power hungry, and expensive than a gate in a CPU (or GPU). modern CPUs excel at executing data-dependent operations of a wide variety while exploiting as much parallelism as available, while GPUs excel at churning through a huge amount of memory doing parallel arithmetic operations: for both of theses tasks an FPGA is going to be worse. For an FPGA to be the better option you need a task which is specialised enough that the speedup from designing a specialised circuit to do it overcomes the intrinsic slowdown from it being implemented in an FPGA as opposed to raw silicon, and these are not your typical software tasks, usually much more hardware-type tasks. The two areas where FPGAs excel are having extremely low and predictable latency, and having lots of extremely flexible high-bandwidth IO (still less bandwidth than the memory or PCI-E bandwidth of a GPU, but it's close and it's much more flexible). For computation throughput, however, there's only a few niche applications, though one important one is simulating the logic which is going to be implemented in a CPU, GPU, or ASIC to validate it before the expensive process of actually etching some silicon.
cpgxiii 4y ago
> The FPGA on the other hand has the output ready one clock cycle after the inputs stream in, and can have many such operations in parallel. One might ask, why are cpus not being replaced by FPGAs? You need to be careful with interpreting cycle counts as execution time. A naive operation on an FPGA may take a single cycle because the author has asked for that, rather than constructing and using a pipelined multi-cycle ALU [1]. Therefore the design tool will synthesize a layout that performs the operation in a single cycle, but the cycle time (and thus clock frequency for that portion of the layout) will be limited by however long that operation needs to complete, and will be much longer than the cycle time of the CPU you are comparing against. Note that a CPU almost certainly has "better" ALUs than those you'd get on an FPGA - optimized fixed-function circuits can always be faster than their generic programmable equivalents - the advantage of the FPGA is that you can have only (and more of) the operations you need, running in parallel as many times as the device will support. You could make a CPU by which every instruction (even very complicated vector instructions like AVX or SVE) was completed entirely in a single cycle, but that cycle itself would be very long, and all of the incredible throughput benefits of pipelined execution would be lost. [1] Pretty much all of the vendor design tools can instantiate an ALU for your device, given parameters like # of bits, operation types, # of cycles, etc.

burnished 4y ago

Neat. If the author is around, might I suggest pushing some of the 'why use an FPGA' to the front? I think it would benefit from a more concrete example motivating the use of an FPGA - like a picture of some simple circuit using a seven segment display on a broad board next to a picture of an FPGA implementing the same circuit in order to make it more clear that it is a substitute for putting experiments together by hand. I think it will help newcomers better contextualize what is happening and why. I think in the same vein your wrap up of why you might want to do something in hardware vs software is great and well placed. Hmmm, I guess now is as good a time as any to bumblefuck around with small electronics projects for fun. Thanks for the reminder!

beardyw 4y ago
> Neat. If the author is around, might I suggest pushing some of the 'why use an FPGA' to the front? I think the problem is identifying cases where you really need an FPGA. Most of the time you don't.
- asdfman123 4y ago
  This is meant to be an introduction though, right? You can simply write “some people do X, and others claim Y is better” then move on. I read several paragraphs of the article and I still don’t know why you’d use one, despite taking computer architecture and analog electronics courses in undergrad. I don’t want to read about logic gates again and I don’t want to read about the nuances before I broadly understand what the point is. For anyone else still wondering, here’s Wikipedia: > FPGAs have a remarkable role in embedded system development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture. Basically, rapid prototyping I guess. That makes sense.
  - awjlogan 4y ago
    If that was an ask for a specific example, one of the most common uses for FPGAs is DSPs. Say you have a simple FIR filter of, say, 63 taps. To do this in a CPU requires you to load two values and do a multiply/accumulate for each tap in sequence. Very (!!) optimistically, that’s about 192 instructions. With an FPGA, you can do all the multiplications in parallel and then just sum the outputs - probably done in 2 cycles and with pipelining your throughput could be a sample every clock. If the FPGA is too slow, too power inefficient etc you can (if you have the money!) take the same core design and put it in an ASIC. The FPGA provides an excellent prototyping environment; in this example you can tune the filter parameters before committing to a full ASIC.

jschveibinz 4y ago

We used them for real time array signal processing and beam-forming. They worked great.

brooksbp 4y ago
super wide AXI-Stream busses?

sph 4y ago

Sadly the article doesn't go into details about how the programmable RAM is wired to the actual logic gates, which seems to me the most interesting and challenging part of designing an FPGA. In my mediocre understanding of digital circuits, RAM is usually addressable, so it has to be wired in a more direct manner to enable such a design. I posted this article because someone mentioned some Ryzen chip having an FPGA in another post, and I am now left wondering: 1. why don't we have more user-programmable FPGAs in our fancy desktop mainboards 2. is there a SoC board, ARM or RISC-V based, with an FPGA on board? The slower the CPU, the more useful an FPGA would be to accelerate compute tasks

MSFT_Edging 4y ago
As for question 1, they're far more common in server grade stuff where typically they are baked in. Consumer stuff just doesn't need/use as much IO throughput and muxing that the FPGA provides on say, a large networking switch. There are PCIe compatible FPGAs that you can plug into your desktop like a graphics card to accelerate certain tasks. In general though, our workstation hardware just isn't specialized enough to require them, but can be extended to do so. If something is a large enough business model, they'll just make an ASIC.
rjsw 4y ago
There are plenty of boards that have one of the combined ARM & FPGA chips, Zynq (Xylinx/AMD) or Cyclone (Altera/Intel).
duskwuff 4y ago
> Sadly the article doesn't go into details about how the programmable RAM is wired to the actual logic gates Not sure what you mean by that. Do you mean how a RAM is used as a lookup table to implement logic gates, how routing works, or how block RAM is integrated into the FPGA fabric? > is there a SoC board, ARM or RISC-V based, with an FPGA on board? Better yet, there are a number of FPGAs available with an ARM SoC on board. Xilinx Zynq, Intel Cyclone V SoC, various others.
wildzzz 4y ago
Both Intel and Xilinx sell FPGAs with hard ARM cores inside so you can run real Linux while being able to interface with custom logic. Additionally, it's pretty common to create ARM, RISC-V, or PowerPC soft cores in the FPGA when there is no hard cores available. These mimic the real cores and will run software while allowing for things like custom instructions that can take advantage of the flexibility of FPGA fabric. The Xilinx Zynq and Intel Cyclone V have options for hard ARM cores. There are various designs of boards out there you can buy that implement Arduino or Raspberry Pi shield compatibility. The XUP PYNQ-Z2 supports both interfaces and runs a Zynq-7000 with a real ARM core. You can do other things with soft cores that are not possible with an off the shelf CPU like triple mode redundancy. This is when you run a lot of the logic in triplicate and vote on the results to prevent a bit flip from messing up the software. This is common for space-based CPUs that are running on FPGAs. It's expensive to design a new chip in a very small run so it's much cheaper to just put the core on an off the shelf FPGA and use the rest of the FPGA fabric for custom logic functions.

markx2 4y ago

If anyone in unaware you can buy the very impressive Pocket. https://www.analogue.co/pocket https://www.analogue.co/pocket The current list of what it can do with FPGA is listed here - https://openfpga-cores-inventory.github.io/analogue-pocket/ https://openfpga-cores-inventory.github.io/analogue-pocket/ and the inevitable sub-reddit is a good resource. https://old.reddit.com/r/AnaloguePocket/ https://old.reddit.com/r/AnaloguePocket/

jonny_eh 4y ago
I also recommend the official dock. It basically turns it into an easy to use Mister.
gchadwick 4y ago
There's also the MiSTer project: https://github.com/MiSTer-devel/Wiki_MiSTer/wiki https://github.com/MiSTer-devel/Wiki_MiSTer/wiki. Not hand-held (yet...) and hardware is less slick but a bunch more systems and also fully open source.
- phendrenad2 4y ago
  MiSTer makes me kind of sad, the DE10-nano board it's based on is 7 years old at this point, and the actual FPGA chip on the board is probably over twice as old as that. And this is still the peak of hobby FPGA chips. I wonder why Moore's Law is hitting the FPGA industry particularly hard all of a sudden.
  - willis936 4y ago
    There are better FPGA options, they're just more expensive. The DE-10 Nano was strategically chosen as "powerful enough to meet most wants while still being within a reasonable budget". No one's going to plunk down $10k for a 19 EV Zynq UltraScale+ with 1.1M LEs, but they will spend $200 on a Cylcone V with 210k LEs.
    - fooblaster 4y ago

dddiaz1 4y ago

Another really cool use case for FPGAs is for ultra fast analysis of genomic data. This guide walks you through setting up an F1 instance (AWS FPGA) to do that: https://aws-quickstart.github.io/quickstart-illumina-dragen/ https://aws-quickstart.github.io/quickstart-illumina-dragen/

nfriedly 4y ago

I've read that AMD's 7040-series mobile CPUs will have an "FPGA-based AI engine developed by Xilinx" [1] - I'm wondering how programmable that will be. I know there's been some performance difficulties emulating the PlayStation 3's various floating point modes. It's the kid of thing that I think an on-chip FPGA could theoretically help with, although I don't know if it'd be worth the trouble in this specific case. (Or if AMD's implementation will be flexible enough to help.) [1]: https://www.anandtech.com/show/18844/amd-unveils-ryzen-mobile-7040u-series-phoenix-to-fly-into-thin-notebooks https://www.anandtech.com/show/18844/amd-unveils-ryzen-mobil...

photochemsyn 4y ago

Here's a nice series that picks up where this one leaves off (shows how flip-flop/LUT units are organized into cells inside a PLB, programmable logic block). It also is the first step in a tutorial on using Verilog, building a hardware finite state machine, and eventually a RISC-V processor on a FPGA: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-1-what-is-an-fpga/3ee5f6c8fa594161a655a9f960060893 https://www.digikey.com/en/maker/projects/introduction-to-fp...

user070223 4y ago

From my understanding FPGA doesn't have the instruction pipeline as the command is encoded in the gates themselves. It means that on runtime the FPGA is not turing complete[0] as opposed to the CPU[1]. There is a phrase "data is code and code is data" in security context. The new saying if FPGA would ever replace cpus' as the main computation hardware(as you don't need turing complete when you keep using the same apps[microservices]) is something like "code is execution and execution is code" as you imprint the code in the gates. It would get rid of a whole class/subclass of memory safety vulernabilitie. This paradigm change is like what webassembly did to the web. The slogan should be "make the bitstream go mainstream" Some made a demo running wasm on fpga[1], not sure if using a cpu or directly of course you move complexity to compiling, and increase loading speed, all for order of magnitude faster execution Companies devloped high level synthesis compilers but it's diffcult and challenging as you need to synchronize parallel excution piplines which you don't have to in cpu since it has steady clock rate for each step in the pipeline A copmany named legup computing(acquired by microchip) compiled memcached/redis applications to fpga and improved perfromance & power efficency by an order of magnitude(10x) There are a lot of intellectual properties in hardware design as opposed to software so tools and knowledge is scarce. If anyone works / want to work on this problem hit me up in the comments [0] Unless you implement a cpu on top of the fpga :) [1] Assuming infinte memory, which is false, but good enough [2] https://github.com/denisvasilik/wasm-fpga https://github.com/denisvasilik/wasm-fpga

proto_lambda 4y ago
> FPGA doesn't have the instruction pipeline as the command is encoded in the gates themselves. It means that on runtime the FPGA is not turing complete[0] as opposed to the CPU[1]. That obviously depends entirely on the circuit, many sufficiently advanced circuits probably end up being accidentally turing complete.
- JohnFen 4y ago
  You can implement turing-complete CPUs in FPGA fabric.
  - 4y ago

mpd 4y ago

I really enjoyed the recent Hackerbox[0] featuring an FPGA. I'd never worked with one prior to that. https://hackerboxes.com/collections/past-hackerboxes/products/hackerbox-0088-fpga-lab https://hackerboxes.com/collections/past-hackerboxes/product...

jokoon 4y ago

So can a large FPGA be somehow used to brute force encryption? I don't really understand electronics to see if a GPU could be faster than a FPGA, but my guess is yes? It seems that anything that can be programmed is inherently slower than a FPGA equivalent doing the same task. Does larger enough key size always defeat a FPGA? I would guess that it becomes power and cost prohibitive for a private company to deliver such possibility, but of course, a large government entity like the NSA might have enough resource to pay for enough FPGA to decrypt most things.

braho 4y ago
Even though the FPGA fabric might encode the solution more effectively, there are other important differentiators: clock speed and memory bandwidth. GPUs have higher clock speeds and typically better memory bandwidth (related of course). With the higher clock speed, GPUs can well outperform FPGAs for many problems.
dreamcompiler 4y ago
> So can a large FPGA be somehow used to brute force encryption? Yes and no. It is usually possible to use an FPGA to build a specific logic circuit that will run some particular algorithm faster than the algorithm would run on a general-purpose CPU. (By a factor of maybe 2x to 100x. It varies a lot depending on the algorithm.) It is also the case that if you implement that algorithm on a dedicated custom chip it can always be designed to run faster than the equivalent FPGA. So if you really want maximum speed, spend the megabucks for dedicated silicon. That said, modern GPUs and DSP chips might be able to run some algorithms almost as fast as dedicated silicon and faster than FPGAs. So maybe you don't need megabucks. Again, it depends on the algorithm. In any case you'd need many orders of magnitude of speedup to usefully brute-force a modern crypto algorithm, and the most you'd get even from dedicated silicon is about three. Useful speedup requires quantum computers -- which don't yet exist -- and even quantum computers will only help break asymmetric crypto, not symmetric crypto.
- jokoon 4y ago
  for AES, for example?

y0ungarmanii 4y ago

I saw various comments about how FPGAs are not ready for consumer hardware, apple is using them in the airpod max already (probably for filtering audio) Check the link below https://www.ifixit.com/Teardown/AirPods+Max+Teardown/139369 https://www.ifixit.com/Teardown/AirPods+Max+Teardown/139369 They really excel for high throughput & low latency - which noise canceling sounds like a good example of! In addition to this, they are already being used in communication systems & data centers to speed up latency sensitive computations. Edge AI seems like a big market that they will be used for soon, probably more likely b/c they can be flashed unlike ASICs and new NN architectures drop every couple of years.

kimburgess 4y ago
There’ll also extremely common in most hardware used for any realtime media processing. With them being mutable it can be updated to support new compression methods, or switched in field to drop a device between acting as an encoder or decoder.

pwpw 4y ago

The MiSTer project[0] is a wonderful open-source introduction to a practical use case for FPGAs. It uses verilog to describe how the DE10-Nano chip should be set up to resemble various classic computers, arcade machines, and video game consoles. With a single device you can have an Apple II+, Super Street Fighter II Turbo, and a SNES. Currently it supports up to the PlayStation for console cores, which is probably the upper bounds for the DE10-Nano. If you want more info, My Life in Gaming has a great overview video[1] of the MiSTer that covers it in depth. The entire project feels perfectly in line with hacker mentality and is exciting to watch grow. There's nothing like playing Super Metroid with an original SNES controller on a CRT at the end of the day. [0] https://github.com/MiSTer-devel/Wiki_MiSTer/wiki https://github.com/MiSTer-devel/Wiki_MiSTer/wiki [1] https://www.youtube.com/watch?v=rhT6YYRH1EI https://www.youtube.com/watch?v=rhT6YYRH1EI

idonotknowwhy 4y ago
Or Time Crisis, with the original light guns on a CRT

deleted 4y ago

[deleted]

qiqitori 4y ago

If anyone's interested in getting into FPGA stuff, the iCE40UP5K (the 5K indicates the number of LUTs; there are other sizes available) has an open-source toolchain that works very well. There are pretty cheap development boards using this FPGA, I use the UPduino, which I bought in 2019 or so. (Recently the same team released a new UPduino dev board that also includes an RP2040, which is probably pretty useful, available at https://lectronz.com/products/pico-ice-rp2040-plus-lattice-ice40up5k-fpga https://lectronz.com/products/pico-ice-rp2040-plus-lattice-i...) What can you do with an FPGA of this size? Not too much, but it's about enough to, for example, fit an implementation of a YM2151 FM audio chip (audio chip from the 80s that was used in synthesizers and arcade machines). I think it would probably also be big enough for old CPUs such as the Z80 or 6502. Unfortunately it's not 5V-tolerant so you can't wire it directly to parts of that era.

yummypaint 4y ago
I second the upduino, it's a great board. Recently i have been using the iCESugar-pro which is also supported by the open source toolchain, and comes in a handy SODIMM form factor that makes it easy to incorporate into real projects. It uses the lattice LFE5U-25F-6BG256C with 24k LUTs and 32 MB SDRAM, 106 usable i/o connections, about $60.

cubefox 4y ago

It seems FPGAs are universal Turing machines (in contrast to ASICs, which are not generally universal), which would make them similar to CPUs. But CPUs are clearly "more universal" in some sense. Perhaps because CPUs can change their programs at run time, which doesn't seem possible for FPGAs. Unfortunately the article doesn't compare FPGAs to CPUs.

agg23 4y ago
That's actually one of the coolest parts about FPGAs. Partial Reconfiguration (Intel docs for example) - https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/partial-reconfiguration.html https://www.intel.com/content/www/us/en/software/programmabl... It's expensive, but it can be very useful.

blopp99 4y ago

I don't know if I'm online on this one but the only thing that have stoped me from finally learning FPGA it's a practical use for me or my Profesional life. I have not yet encounter a situation besides the bucket list item of making a chip, which btw I don't even need to know FPGA at this point to complete this, that has made me seriously sit and Lear FPGA

bschwindHN 4y ago

Is there a good "starter" FPGA kit which has an open-source toolchain, and the ability to build/deploy everything from the command line? I'm going through links in the comments here now in search of this too. It would be cool to hook up an FPGA to an image sensor and do my own processing from the raw sensor data. Based on that description, I'm not sure which dev board or starter kit would be best to be looking at.

xkriva11 4y ago
look for example at iCESugar-nano, low spec but fits your requirements https://github.com/wuxx/icesugar-nano https://github.com/wuxx/icesugar-nano
- bschwindHN 4y ago
  Oh this looks perfect, thanks! Here's one more thing I don't know - how do you evaluate whether or not an FPGA is sufficient for what you want to do? For example, let's say I want to talk to an image sensor which has a 3088x2076 resolution, and either capture still images or maybe video at some frame rate. Which specs do I need to hone in on and evaluate to determine which FPGAs would work, and which won't?

JohnMakin 4y ago

these are much cheaper to produce and run, not to mention more flexible than GPU’s for LLM training. as an added benefit you can write (if you were so inclined) hardware-level logic to whatever workload you want. reprogrammable as well. -background : 4-5 years ago worked on embedded systems tech that used these for fintech. they seemed like the future back then and LLM workloads were barely a thing. Glad more people are learning about them.

djmips 4y ago

People should make their software faster before they turn to FPGAs. Unless you already did that! But FPGA is a lot of fun to learn and play with even if you don't have a ready application.

yummypaint 4y ago
On the other hand, there are fpga boards priced comparably to microcontrollers now. It can be very refreshing and useful to escape the "programming" paradigm. Hobbyists are already contributing the value of their time which is generally much larger than the cost difference between device types, so in a sense the fpga barrier to entry may actually be higher for companies than individuals at the moment.

kepler1 4y ago

Although it was a little bit of a long way to get to a point, I did somewhat appreciate the article's going into the idea of the circuit structure and look up tables. It made me think (and I don't know if this is an apt analogy), it's like if you have 2 versions of a machine responsible for sorting different size balls in a factory. One of them (#1) is built with pipes that exactly encode (in hardware, like a grid of holes) which balls are allowed to pass which size buckets on a production line. The other (#2) uses a robot that looks at each ball passing by, does some measurements, and decides whether it's the right size for a certain bucket. (#1) is not very flexible, but is really great at the job and can do it just by shaking the tray and works for thousands of balls at once. (#2) needs to take time to study each one passing by. But you can reprogram it more easily. Each has its purpose. And the FPGA tries to give you the advantages of #1 with a bit more flexibility to change the size of the holes, etc. Then, replace balls with input video files that need an efficient decoder in hardware, etc. and I see the link.

Eumenes 4y ago

Great overview. I do wonder if FPGAs will make a run against modern server/GPU cluster setups for AI/ML.