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Could someone please explain why they can't just hire equipment from a university lab if all they want to make are small batches using old processes? Aren't the

Could someone please explain why they can't just hire equipment from a university lab if all they want to make are small batches using old processes? Aren't there lots of commercial-use programs for university equipment? For example In Bradford, UK, there is(was years when I was there) a whole building full of startups taking advantage of the university in the medical field. For anyone that thinks universities support only cutting edge research let me say one startup I did some work for there was testing anti-acne drugs on cell cultures. Definitely not cutting edge stuff. On the electronics side there is another org nearby (Electronics Yorkshire) where you can hire really expensive inspection equipment (like 3d xray machines etc) by the hour. This is not their core business, but it is a very useful service for startups in aero-space electronics for example. I can't imagine there are no equivalent organisations and university programs in US.

riffraff 4y ago
isn't the point that they want to innovate on the equipment?
alted 4y ago
I do research in a university lab that is also used by a number of companies. People make plenty of transistors, including state-of-the-art research. However, reasonably sized processors need millions of transistors, and (a) we can't easily make that many at competitive feature sizes, (b) it takes significant time and effort to set up and debug a process, and even more to get high yield. So while it's theoretically possible to make small processors, it's much easier (and, including labor, probably cheaper) to leave that to dedicated fabs. Small prototyping runs (via [1] or similar) are common. Instead, people use the lab to, e.g., prototype new MEMS devices or test new types of transistors or memory cells. Once the technology is proven, it can be mass-produced elsewhere. [1] https://www.musesemi.com/ https://www.musesemi.com/
bippingchip 4y ago
There are 2 main difference between many university (and even the much larger dedicated research lab/fabs like for example in Albany/NY Creates): - Research labs are typically equipped to focus on critical parts of the overal production process they want to do research on. But to get actual designs manufactured you need a fully working and sufficiently yielding process from bare wafers to transistors, interconnect, passivation etc. This is easily multiple hundreds of steps to 1000+ different process steps (just think about making a single metal layer: deposit resist, expose, etch, deposit barrier, liner and and then metal, CMP) This works well for the uses cases you describe: dedicated inspection equipment or very niche small scale nano fabrication needed. But making a a fully working VLSI CMOS process needs much higher complexity and many more different process steps and equipment. Which brings me to the second point: - Research labs typically don't care much about yield: they need sufficient amount of working devices to measure and show things are possible and publish about it, but they do not need to bring it up to reliably reproducible results. However when you make an ASIC with millions to billons of transistors and wires, you typically depend on ALL vias and ALL transistors working, not just 80-90% of them, to get a functional chip. This is a lot of hard and dedicated work, in a way it's an art, black magic almost to most: very few people and companies have the expertise to pull this off. It's not a big exaggeration to say only TSMC can do this really well. Just look at how much even Intel is struggling to get their next node out (it's been how many years of Tick Tock Tock Tock Tock.. now?)
- lloydatkinson 4y ago
  Does what you've written here apply to UK universities too though?
- Roark66 4y ago
  That's a good argument /explanation. However, based on the equipment cost they mentioned (half a million $) I assumed they wouldn't be doing VLSI chips. As you said process reliability and efficiency is king there. I very much doubt you can do VLSI chips with alibaba equipment for $0.5million. My impression was they would be making rare chips with few tens of transistors tops (perhaps analog ics etc.). Even with few dozen transistors there should be many chips they could sell. Simple(obsolete) logic no one makes, but required to service old military equipment. Other simple IC's. If they could pull off a process to produce few K of transistors efficiently (an equivalent of 1980s tech) they could make microcontrollers etc(flash is another story). This is coming into VLSI territory, but it is still extremely far from a powerfull TPU chip. Look at google's edge TPU. I bet they sell them so cheap only because they had some unused wafer space left near the edges when making their proper TPUs. So they squeezed in some of those edge TPUs almost for free. How can anyone with alibaba equipment compete with that?
  - Robotbeat 4y ago
    Sam Zeloof did a 1000 transistor chip (granted, not interconnected) with eBay Alibaba type stuff. VLSI would be probably 10,000 transistors or higher, so within the realm of possibility.
- joshvm 4y ago
  On the thousand steps bit, LTT did a tour of one of Intel's fabs in Israel and it's pretty incredible. Everything is automated with little bins moved via overhead rails to the different stations. https://www.youtube.com/watch?v=2ehSCWoaOqQ https://www.youtube.com/watch?v=2ehSCWoaOqQ
lofatdairy 4y ago
I can't fully answer this question bc I'm not in the sc fab field but afaik for most medical research you're not needing to get down the nano-scale yourself. Unless you're designing/building custom chips for imaging or bci's, but even then I imagine any in-house prototyping is not at the final scale. In the US there's a consortium of fabrication centers[^1], but even if a uni has a clean room, I think a lot of custom designs often go through China because it's less hassle. [^1]: https://nnci.net/sites/view-all https://nnci.net/sites/view-all
- namibj 4y ago
  Do you have any further information on how/if there are "practical" ways to get custom maskless VLSI there? Due to the practical limitations on "direct" reticle size for maskless lithography, you already need reticle stitching for matching any modern (think, this century) mask-based photolithography VLSI capabilities, and thankfully most maskless reticle stitching tactics can be scaled to an entire wafer. [0] Some tactics likely need mechanical re-positioning of the write head to different parts of the wafer due to Etendue limitations of commercially practical optics (keeping sharp focus across the entire optically reachable area, within which they rapidly write individual reticles at reticles-per-second rates IIUC usually somewhere in the audible range), but the same mechanism that's used to track alignment of the lithography layer to those of previous steps, can typically be adapted to work across mechanical scanning within exposure of the same lithography layer. While wafer-scale integration naturally needs defect-compensation, modern micro-channel liquid/phase-change cooling can already handle heat removal at desktop Zen3 chiplet power densities without needing a heat spreader to thin the power density out. Tactics like feeding in the liquid parallel to the chip, and letting it boil on the chip-side of the structure, to then let the vapor escape normal to the chip (if it's flat, this would be vertically upwards), can scale to very large areas because you can put occasional liquid feed pipes in the vapor-space that are thick enough to not cause excessive pressure loss, and thus scale from having to pass the liquid sideways across the entire chip to something with less flow resistance (pressure drop) for the escaping vapor. 3D printing can manufacture those intricate structures that allow exceeding areal power density limits of nucleate boiling (which are around 10~30 W/cm² for chemically/environmentally tame hydrocarbons (e.g. Pentane, boiling comfortably at 1bar/2bar/5bar at, respectively, 36°C/58°C/92°C, low toxicity but more flammable than gasoline), and around 100 W/cm² for water (sadly, 120°C surface temperature isn't practical for silicon CPUs)). Wafer-scale processors are just extremely capable compared to normal reticle-limited ones, see e.g. how Cerebras manages to run fluid dynamics simulations for things like iirc helicopters at/above realtime speeds, enabling predictive control in aerodynamically unstable situations. Allowing manufacture of processors not limited to special reticle-border-crossing wires is, IMO, quite ground-breaking. Imagine things like hex or triangle grid mesh networks on the chip, and just overall a far more homogenous mesh topology just about flexible enough to route around the defects, possibly using just the normal required back-pressure routing to deal with the congestion-hotspot from needing to divert around a disabled cell (and do so without the greater surroundings needing to even be aware of that cell being disabled). [At worst a disabled area would need to be turned into a rectangle to make adaptive Manhattan routing work. The software would need to be taught to deal with holes in the physical-location-based address space, but many algorithms are inherently tolerant enough to deliver proper useful results even with their data grid having holes/crystal defects, and a physically homogenous grid of cores (should, IMO) fit(s) those better than one less-homogenous that can fully mask deactivated cores (like Cerebras's device).] And beyond wafer-scale processors, analog VLSI processors (they could be manufactured using traditional photolithography) are awesome. There are just two major obstacles in the way of utilizing them: 1) they don't allow much flexibility in even simple operating parameter tuning (let alone larger FPGA-like reconfiguration) to use a generic chip in many situations/different devices. Thus they need a low practical MOQ for broad utilization. 2) due to difficulty with simulating/modeling the entire dynamic system they operate/control, substantial iterative experimental tuning of the hard-coded (though literally the shapes of the devices manufactured in the integrated circuit) parameters will be necessary during product development. Mask-less lithography is inherently able to manufacture down to single-digit MOQs (only really limited by stochastic yield/binning and multi-step-process lead times). [It's trivial to sample the hard-coded tuning parameter space, via simulating behavior differences, and then sampling finely enough to not miss the perfect range of parameter values as a result of manufacturing yield/rejects poking holes into the sampling grid.] I believe there are substantial opportunities in electronic power converters, due to the frequencies unlocked by recent advances in [high-frequency-capable] SiC and GaN power transistors. And how multi-MHz switching shrinks the size of capacitors/inductors/transformers, in exchange for demanding extremely rapid control (and worse, often limiting the current of a single module due to speed-of-light effects, which implies many individual controller chips). For reference, here's a list of commonly-encountered electronic power converters that typically aren't made in the quantities needed to make traditional analog/mixed ASICs economically feasible: "computer power supply", "high-efficiency electronic motor controller" (which are just fancy variable power supplies commanded by a controller that translates input commands and possibly sensor feedback into drive voltages), "solar panel to power grid adapter" (regardless of whether the grid is a normal AC grid needing it to be an inverter, or if it's a DC grid needing it to only adapt the voltage), "battery charger" (essentially all types, except if the voltage matching is done by an external device like how electric cars with DC fast charging only request the desired voltage from the stationary "charger" (itself "just" a variable power supply)), etc. [0]: [With DLP chips, you get single-exposure pixel counts on the same scale as contemporary TFT (I e., active, large-panel) LCDs (the kind used in flat screen computer monitors and TVs; this stems from a large (if not the largest) market for DLP technology being projectors/beamers), and electron-beam approaches run into issues with deflection mechanism linearity (i.e., pixel spacing uniformity between center and borders) in the 1000~100000 (1k~100k) linear pixels (width, in the fast axis).]

riffraff 4y ago

isn't the point that they want to innovate on the equipment?

alted 4y ago

I do research in a university lab that is also used by a number of companies. People make plenty of transistors, including state-of-the-art research. However, reasonably sized processors need millions of transistors, and (a) we can't easily make that many at competitive feature sizes, (b) it takes significant time and effort to set up and debug a process, and even more to get high yield. So while it's theoretically possible to make small processors, it's much easier (and, including labor, probably cheaper) to leave that to dedicated fabs. Small prototyping runs (via [1] or similar) are common. Instead, people use the lab to, e.g., prototype new MEMS devices or test new types of transistors or memory cells. Once the technology is proven, it can be mass-produced elsewhere. [1] https://www.musesemi.com/ https://www.musesemi.com/

bippingchip 4y ago

There are 2 main difference between many university (and even the much larger dedicated research lab/fabs like for example in Albany/NY Creates): - Research labs are typically equipped to focus on critical parts of the overal production process they want to do research on. But to get actual designs manufactured you need a fully working and sufficiently yielding process from bare wafers to transistors, interconnect, passivation etc. This is easily multiple hundreds of steps to 1000+ different process steps (just think about making a single metal layer: deposit resist, expose, etch, deposit barrier, liner and and then metal, CMP) This works well for the uses cases you describe: dedicated inspection equipment or very niche small scale nano fabrication needed. But making a a fully working VLSI CMOS process needs much higher complexity and many more different process steps and equipment. Which brings me to the second point: - Research labs typically don't care much about yield: they need sufficient amount of working devices to measure and show things are possible and publish about it, but they do not need to bring it up to reliably reproducible results. However when you make an ASIC with millions to billons of transistors and wires, you typically depend on ALL vias and ALL transistors working, not just 80-90% of them, to get a functional chip. This is a lot of hard and dedicated work, in a way it's an art, black magic almost to most: very few people and companies have the expertise to pull this off. It's not a big exaggeration to say only TSMC can do this really well. Just look at how much even Intel is struggling to get their next node out (it's been how many years of Tick Tock Tock Tock Tock.. now?)

lloydatkinson 4y ago
Does what you've written here apply to UK universities too though?
Roark66 4y ago
That's a good argument /explanation. However, based on the equipment cost they mentioned (half a million $) I assumed they wouldn't be doing VLSI chips. As you said process reliability and efficiency is king there. I very much doubt you can do VLSI chips with alibaba equipment for $0.5million. My impression was they would be making rare chips with few tens of transistors tops (perhaps analog ics etc.). Even with few dozen transistors there should be many chips they could sell. Simple(obsolete) logic no one makes, but required to service old military equipment. Other simple IC's. If they could pull off a process to produce few K of transistors efficiently (an equivalent of 1980s tech) they could make microcontrollers etc(flash is another story). This is coming into VLSI territory, but it is still extremely far from a powerfull TPU chip. Look at google's edge TPU. I bet they sell them so cheap only because they had some unused wafer space left near the edges when making their proper TPUs. So they squeezed in some of those edge TPUs almost for free. How can anyone with alibaba equipment compete with that?
- Robotbeat 4y ago
  Sam Zeloof did a 1000 transistor chip (granted, not interconnected) with eBay Alibaba type stuff. VLSI would be probably 10,000 transistors or higher, so within the realm of possibility.
joshvm 4y ago
On the thousand steps bit, LTT did a tour of one of Intel's fabs in Israel and it's pretty incredible. Everything is automated with little bins moved via overhead rails to the different stations. https://www.youtube.com/watch?v=2ehSCWoaOqQ https://www.youtube.com/watch?v=2ehSCWoaOqQ

lofatdairy 4y ago

I can't fully answer this question bc I'm not in the sc fab field but afaik for most medical research you're not needing to get down the nano-scale yourself. Unless you're designing/building custom chips for imaging or bci's, but even then I imagine any in-house prototyping is not at the final scale. In the US there's a consortium of fabrication centers[^1], but even if a uni has a clean room, I think a lot of custom designs often go through China because it's less hassle. [^1]: https://nnci.net/sites/view-all https://nnci.net/sites/view-all

namibj 4y ago
Do you have any further information on how/if there are "practical" ways to get custom maskless VLSI there? Due to the practical limitations on "direct" reticle size for maskless lithography, you already need reticle stitching for matching any modern (think, this century) mask-based photolithography VLSI capabilities, and thankfully most maskless reticle stitching tactics can be scaled to an entire wafer. [0] Some tactics likely need mechanical re-positioning of the write head to different parts of the wafer due to Etendue limitations of commercially practical optics (keeping sharp focus across the entire optically reachable area, within which they rapidly write individual reticles at reticles-per-second rates IIUC usually somewhere in the audible range), but the same mechanism that's used to track alignment of the lithography layer to those of previous steps, can typically be adapted to work across mechanical scanning within exposure of the same lithography layer. While wafer-scale integration naturally needs defect-compensation, modern micro-channel liquid/phase-change cooling can already handle heat removal at desktop Zen3 chiplet power densities without needing a heat spreader to thin the power density out. Tactics like feeding in the liquid parallel to the chip, and letting it boil on the chip-side of the structure, to then let the vapor escape normal to the chip (if it's flat, this would be vertically upwards), can scale to very large areas because you can put occasional liquid feed pipes in the vapor-space that are thick enough to not cause excessive pressure loss, and thus scale from having to pass the liquid sideways across the entire chip to something with less flow resistance (pressure drop) for the escaping vapor. 3D printing can manufacture those intricate structures that allow exceeding areal power density limits of nucleate boiling (which are around 10~30 W/cm² for chemically/environmentally tame hydrocarbons (e.g. Pentane, boiling comfortably at 1bar/2bar/5bar at, respectively, 36°C/58°C/92°C, low toxicity but more flammable than gasoline), and around 100 W/cm² for water (sadly, 120°C surface temperature isn't practical for silicon CPUs)). Wafer-scale processors are just extremely capable compared to normal reticle-limited ones, see e.g. how Cerebras manages to run fluid dynamics simulations for things like iirc helicopters at/above realtime speeds, enabling predictive control in aerodynamically unstable situations. Allowing manufacture of processors not limited to special reticle-border-crossing wires is, IMO, quite ground-breaking. Imagine things like hex or triangle grid mesh networks on the chip, and just overall a far more homogenous mesh topology just about flexible enough to route around the defects, possibly using just the normal required back-pressure routing to deal with the congestion-hotspot from needing to divert around a disabled cell (and do so without the greater surroundings needing to even be aware of that cell being disabled). [At worst a disabled area would need to be turned into a rectangle to make adaptive Manhattan routing work. The software would need to be taught to deal with holes in the physical-location-based address space, but many algorithms are inherently tolerant enough to deliver proper useful results even with their data grid having holes/crystal defects, and a physically homogenous grid of cores (should, IMO) fit(s) those better than one less-homogenous that can fully mask deactivated cores (like Cerebras's device).] And beyond wafer-scale processors, analog VLSI processors (they could be manufactured using traditional photolithography) are awesome. There are just two major obstacles in the way of utilizing them: 1) they don't allow much flexibility in even simple operating parameter tuning (let alone larger FPGA-like reconfiguration) to use a generic chip in many situations/different devices. Thus they need a low practical MOQ for broad utilization. 2) due to difficulty with simulating/modeling the entire dynamic system they operate/control, substantial iterative experimental tuning of the hard-coded (though literally the shapes of the devices manufactured in the integrated circuit) parameters will be necessary during product development. Mask-less lithography is inherently able to manufacture down to single-digit MOQs (only really limited by stochastic yield/binning and multi-step-process lead times). [It's trivial to sample the hard-coded tuning parameter space, via simulating behavior differences, and then sampling finely enough to not miss the perfect range of parameter values as a result of manufacturing yield/rejects poking holes into the sampling grid.] I believe there are substantial opportunities in electronic power converters, due to the frequencies unlocked by recent advances in [high-frequency-capable] SiC and GaN power transistors. And how multi-MHz switching shrinks the size of capacitors/inductors/transformers, in exchange for demanding extremely rapid control (and worse, often limiting the current of a single module due to speed-of-light effects, which implies many individual controller chips). For reference, here's a list of commonly-encountered electronic power converters that typically aren't made in the quantities needed to make traditional analog/mixed ASICs economically feasible: "computer power supply", "high-efficiency electronic motor controller" (which are just fancy variable power supplies commanded by a controller that translates input commands and possibly sensor feedback into drive voltages), "solar panel to power grid adapter" (regardless of whether the grid is a normal AC grid needing it to be an inverter, or if it's a DC grid needing it to only adapt the voltage), "battery charger" (essentially all types, except if the voltage matching is done by an external device like how electric cars with DC fast charging only request the desired voltage from the stationary "charger" (itself "just" a variable power supply)), etc. [0]: [With DLP chips, you get single-exposure pixel counts on the same scale as contemporary TFT (I e., active, large-panel) LCDs (the kind used in flat screen computer monitors and TVs; this stems from a large (if not the largest) market for DLP technology being projectors/beamers), and electron-beam approaches run into issues with deflection mechanism linearity (i.e., pixel spacing uniformity between center and borders) in the 1000~100000 (1k~100k) linear pixels (width, in the fast axis).]