3 ms·
Their node disadvantage is mostly good marketing from TSMC though. Intel 10 (10nm, but that's not the real nanometers) is ~100M transistors per mm2, while TSMC
by reisse 4y ago
Their node disadvantage is mostly good marketing from TSMC though. Intel 10 (10nm, but that's not the real nanometers) is ~100M transistors per mm2, while TSMC 5 (5nm, but again, that's not the real nanometers) is ~130M transistors per mm2.
Sure, 30% better, but not a 2x improvement as marketing suggests.
- megous 4y ago10nm to 5nm feature size should be [naively thinking] 4x improvement in density, so it's even worse. :)
- paulmd 4y agoActual feature size stopped shrinking a long time ago, though. First they flipped the transistors on their side (FinFET) and now they're embedding them inside a block of gate (GAAFET) to get more out of the same size. But the transistors have not just diverged from their actual names (which happened a long time ago) but have not even really shrunk since like 28nm, there is no dimension of a 5nm chip that is actually 5nm. ;) I know you're poking fun at it, but, node names are completely made up and the points don't matter these days. It is a "5nm-class node", if nodes had continued to shrink according to the original plans in 2000 or whatever.
- Dylan16807 4y agoI will nitpick because the naming is a giant mess: There is no "Intel 10". Intel's old naming scheme had "nm" after every number, and the one you're describing is "10nm". Then they renamed everything to use smaller numbers, and no "nm". Newer versions of "10nm" became "Intel 7", still at ~100M transistors per mm². Similarly "7nm" became "Intel 4", with an expected density of ~160M. And so on.
- 7speter 4y agoA bit of an efficiency advantage though, as seen when you max out zen4 vs alderlake/raptorlake cpus.