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>The Xilinix development environment is Vivado which supports writing and compiling your HDL along with creating testbenches and running simulations. I tried g

by ginko 4y ago

>The Xilinix development environment is Vivado which supports writing and compiling your HDL along with creating testbenches and running simulations. I tried getting into FPGA development, played around a bit with simple Verilog implementations then got a cheap FPGA board an pretty much failed at Vivado. That tool is completely unusable. It makes me think of 90s Visual studio where you have to jump through 5 forms and wizards to generate a broken project that wouldn't compile or run on your board. Are there shell tools for FPGA programming you can just set up with a Makefile or something? Having to use a GUI for stuff like this seems silly to me.

rowanG077 4y ago
Yes, yosys + nextpnr for example. But you have to pick an FPGA that is supported.
- mwbajor 4y ago
  Yosys is nice, but you aren't going to get around using vendors tools for configuring IP unfortunately. Vendors stopped supporting 3rd party tools a few years ago primarly because it was so hard to integrate the IP configuration. For instance, the last time I used Synopsys' tool (Synplyfy) I had to always have ISE or Vivado open in another window to configure IP. Of course, for many things, you might not need to configure vendor IP. Examples where you most definitely need to are 1) Filters, 2) FFTs, 3) DDR controllers 4) High speed transceivers. In some cases you can configure vendor IP with language templates. If you don't need these components, then Yosys will be good for you.
  - deleted 4y ago
    [deleted]
Gracana 4y ago
The proprietary tools are painful! I never really used FPGAs outside of school until there were other options. Look at the open source yosys/nextpnr toolchain. Your best bet is to use lattice ice40 or ecp5 FPGAs with it, they’re very well supported.
mwbajor 4y ago
Yes and no. You can stitch a toolchain together using these tools: opencircuitdesign.com, yosys, openlane But if you just want to get up and running with a dev board, use Vivado (for xilinx) and Quartus for altera. Neither are great. For Vivado, use a release that ends in a X.4 unless you want to bang your head against the wall for a few hours. If you are not liking the graphical flow for Vivado, you can definitely just write your VHDL or Verilog and compile it without the need for "block diagrams" ,etc. Vivado calls it the "non project" flow I believe and thats what most of us in industry use. Most people in industry use the Vendor tools. A few years ago you could get 3rd party tools but they weren't much better. The open source toolchains are coming along but still not for the beginner. The vendors will make their libraries more like foundry PDKs soon though and open source 3rd party tools will hopefully finally take off.
bogantech 4y ago
It's possible to run the Xilinx tools using a Makefile, If you don't want to use Xilinx tools at all there's Yosys but you'd have to check if it supports the device you're targeting. There's an example of using a makefile for Vivado here: https://github.com/hdlguy/make_for_vivado https://github.com/hdlguy/make_for_vivado
gchadwick 4y ago
Check out https://github.com/olofk/fusesoc https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
lnsru 4y ago
Vivado can be used with tcl commands without looking at GUI. That’s how things are automated. It might take a while to understand what’s happening in background though: https://docs.xilinx.com/v/u/2019.2-English/ug835-vivado-tcl-commands https://docs.xilinx.com/v/u/2019.2-English/ug835-vivado-tcl-... Don’t worry, it’s not for everybody. It looks like other code, but it isn’t your casual code. I do it for more than decade, colleagues from other groups come me, I teach, they try and never come back.
CorrectHorseBat 4y ago
Yes, Xilinx calls it batch mode. It's much better, but still sucks.
tails4e 4y ago
I really like vivado. Compared with ASIC EDA tools it's amazing. Perjaps it's my EE and ASIC deign background that colours my impression of it, but I've found it works really well. I especially like using the elaborated design view for exploring my RTL structure. What specifically did not work for you?
- thinknubpad 4y ago
  [dead]
cmrdporcupine 4y ago
Yep. For whatever reason, hardware engineers seem to be suckers for punishment and seem to be willing to put up with whatever terrible fork of Eclipse every HW vendor wants to hoist on them this year. In fact they seem to demand it. That said, all the stuff inside the Vivado pkg is scriptable through Tcl. When I was playing with this stuff... Between that and Fusesoc + some hooks with CMake + Verilog mode in CLion I was able to get a fairly reasonable working environment that wasn't totally awful. Still had to dump out into Vivado here and there to configure various "IP" blocks (and then take the generated Tcl and clean it up and import it into proper source control)
variadix 4y ago
Ironically, Xilinx’s tool chain is probably the best of the large FPGA manufacturers. It does leave a lot to be desired compared to software tool chains.
phendrenad2 4y ago
I don't understand why FPGA dev tools are so, so incredibly terrible. 100GB+ install size, hour-long compilation for trivial projects, random glitches you can only fix by restarting the IDE, other random glitches that corrupt your project files (hope you keep backups!), clunky slow GUI that randomly crashes to desktop, the requirement that you pay $x,xxx/year to use a $xxx dev board. It was a fun hobby for awhile, but I gave up and left it behind.
- imtringued 4y ago
  The huge installation size must be related to the size and quantity of FPGAs that are supported. It wouldn't surprise me if those 10 million LUT FPGAs end up bloating it up for the every day hobbyist. Some form of modularity would be welcome.
  - phendrenad2 4y ago
    They are modular. At least, last time I checked. You can pick and choose which FPGAs you want to support when you install the vendor's tools. But even if you remove support for all but one model of FPGA chip, it's still a very large install. And if you expand that to one entire FPGA family (maybe 100 or so chip models), that jumps it up by 50GB easily. So 500MB per FPGA model. And these models are highly similar within the same family, they just have different numbers of LUTs and layouts. My hopeful theory is that they're doing some kind of per-device precomputation that helps accelerate placing & routing. The theory I actually believe in is that they're just duplicating lots of data unnecessarily, and don't see any value prospect in fixing it.

by ginko 4y ago

rowanG077 4y ago

Yes, yosys + nextpnr for example. But you have to pick an FPGA that is supported.

mwbajor 4y ago
Yosys is nice, but you aren't going to get around using vendors tools for configuring IP unfortunately. Vendors stopped supporting 3rd party tools a few years ago primarly because it was so hard to integrate the IP configuration. For instance, the last time I used Synopsys' tool (Synplyfy) I had to always have ISE or Vivado open in another window to configure IP. Of course, for many things, you might not need to configure vendor IP. Examples where you most definitely need to are 1) Filters, 2) FFTs, 3) DDR controllers 4) High speed transceivers. In some cases you can configure vendor IP with language templates. If you don't need these components, then Yosys will be good for you.
- deleted 4y ago
  [deleted]

Gracana 4y ago

The proprietary tools are painful! I never really used FPGAs outside of school until there were other options. Look at the open source yosys/nextpnr toolchain. Your best bet is to use lattice ice40 or ecp5 FPGAs with it, they’re very well supported.

mwbajor 4y ago

Yes and no. You can stitch a toolchain together using these tools: opencircuitdesign.com, yosys, openlane But if you just want to get up and running with a dev board, use Vivado (for xilinx) and Quartus for altera. Neither are great. For Vivado, use a release that ends in a X.4 unless you want to bang your head against the wall for a few hours. If you are not liking the graphical flow for Vivado, you can definitely just write your VHDL or Verilog and compile it without the need for "block diagrams" ,etc. Vivado calls it the "non project" flow I believe and thats what most of us in industry use. Most people in industry use the Vendor tools. A few years ago you could get 3rd party tools but they weren't much better. The open source toolchains are coming along but still not for the beginner. The vendors will make their libraries more like foundry PDKs soon though and open source 3rd party tools will hopefully finally take off.

bogantech 4y ago

It's possible to run the Xilinx tools using a Makefile, If you don't want to use Xilinx tools at all there's Yosys but you'd have to check if it supports the device you're targeting. There's an example of using a makefile for Vivado here: https://github.com/hdlguy/make_for_vivado https://github.com/hdlguy/make_for_vivado

gchadwick 4y ago

Check out https://github.com/olofk/fusesoc https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).

lnsru 4y ago

Vivado can be used with tcl commands without looking at GUI. That’s how things are automated. It might take a while to understand what’s happening in background though: https://docs.xilinx.com/v/u/2019.2-English/ug835-vivado-tcl-commands https://docs.xilinx.com/v/u/2019.2-English/ug835-vivado-tcl-... Don’t worry, it’s not for everybody. It looks like other code, but it isn’t your casual code. I do it for more than decade, colleagues from other groups come me, I teach, they try and never come back.

CorrectHorseBat 4y ago

Yes, Xilinx calls it batch mode. It's much better, but still sucks.

tails4e 4y ago

I really like vivado. Compared with ASIC EDA tools it's amazing. Perjaps it's my EE and ASIC deign background that colours my impression of it, but I've found it works really well. I especially like using the elaborated design view for exploring my RTL structure. What specifically did not work for you?

thinknubpad 4y ago
[dead]

cmrdporcupine 4y ago

Yep. For whatever reason, hardware engineers seem to be suckers for punishment and seem to be willing to put up with whatever terrible fork of Eclipse every HW vendor wants to hoist on them this year. In fact they seem to demand it. That said, all the stuff inside the Vivado pkg is scriptable through Tcl. When I was playing with this stuff... Between that and Fusesoc + some hooks with CMake + Verilog mode in CLion I was able to get a fairly reasonable working environment that wasn't totally awful. Still had to dump out into Vivado here and there to configure various "IP" blocks (and then take the generated Tcl and clean it up and import it into proper source control)

variadix 4y ago

Ironically, Xilinx’s tool chain is probably the best of the large FPGA manufacturers. It does leave a lot to be desired compared to software tool chains.

phendrenad2 4y ago

I don't understand why FPGA dev tools are so, so incredibly terrible. 100GB+ install size, hour-long compilation for trivial projects, random glitches you can only fix by restarting the IDE, other random glitches that corrupt your project files (hope you keep backups!), clunky slow GUI that randomly crashes to desktop, the requirement that you pay $x,xxx/year to use a $xxx dev board. It was a fun hobby for awhile, but I gave up and left it behind.

imtringued 4y ago
The huge installation size must be related to the size and quantity of FPGAs that are supported. It wouldn't surprise me if those 10 million LUT FPGAs end up bloating it up for the every day hobbyist. Some form of modularity would be welcome.
- phendrenad2 4y ago
  They are modular. At least, last time I checked. You can pick and choose which FPGAs you want to support when you install the vendor's tools. But even if you remove support for all but one model of FPGA chip, it's still a very large install. And if you expand that to one entire FPGA family (maybe 100 or so chip models), that jumps it up by 50GB easily. So 500MB per FPGA model. And these models are highly similar within the same family, they just have different numbers of LUTs and layouts. My hopeful theory is that they're doing some kind of per-device precomputation that helps accelerate placing & routing. The theory I actually believe in is that they're just duplicating lots of data unnecessarily, and don't see any value prospect in fixing it.