11 ms·
What happens when a CPU starts
- tim_hutton 4y agoOne route to understanding how CPUs work is to explore the computers that have been made in cellular automata. Golly (https://golly.sourceforge.net/ https://golly.sourceforge.net/) has several, including one by John von Neumann, one by Edgar Codd and another by John Devore. The advantage of course is that the physics is trivial and you can see everything that happens and step backwards and forwards. Example: https://timhutton.github.io/2010/03/10/30984.html https://timhutton.github.io/2010/03/10/30984.html https://github.com/GollyGang/ruletablerepository/wiki/CoddsDesign https://github.com/GollyGang/ruletablerepository/wiki/CoddsD...
- storklathe 4y agoCould anybody clarify for me the purpose of the NOP opcode that the article refers to? I would think that something like a "do nothing" instruction would want to be optimized away as much as possible, but maybe there's some hidden facet of the instruction protocol I'm not familiar with that necessitates it?
- fennecfoxy 4y agoI don't know how much it's really used these days, but when I've done asm stuff before if you have tight timing requirements in assembly, say you're bit banging an IO for some arcane serial protocol a la WS281X LED series, where it doesn't use a hardware supported serial protocol like SPI (where you can just DMA what you want to send to the controller) you then have to implement this protocol manually, in code, switching the IO pin on & off according to the timing requirements of said serial protocol/what data you want to send. For the purposes of this, the nop instruction is useful as it's a great way to delay the processor for 1 instruction at a time and given you know the clock speed and therefore instructions per second you can: * Set the IO high * Use nops (or other instructions) to waste time * Set the IO low This is very useful in situations where the timing needs to be too precise to use interrupts, which are somewhat unpredictable. Obviously this means an entire CPU is held up running this code. Another timing usage is for generating a signal to display a picture on a CRT using a microcontroller. Plenty of others as well. Personally, though, I would never bother. It's always better to get a dedicated chip/controller for something like driving those stupid LEDs (or just get an SPI LED) or to generate a TV signal. Reading up on it further, apparently it is also used as a way to reserve space in code memory, I imagine for self-modifying code (ie fill with nops which can be replaced with actual instructions by your code, depending on code execution). But I've never actually done this myself.
- seanw444 4y agoI believe you can get a good idea for using NOPs if you watch Ben Eater's video on implementing the RS-232 protocol.
- storklathe 4y agoThank you so much, that makes perfect sense!
- fennecfoxy 4y agoI think this is traditional for this topic: https://nandgame.com/ https://nandgame.com/ Say goodbye to a couple hours!
- miga 4y agoIt describes old 8-bit machines. New machines start by executing instructions firmware ROM or in cache memory before RAM is tested and initialized. Additionally the reset registers differ by the platform. (Some platforms expect software to initialize and reset some registers.)
- pclmulqdq 4y ago"It starts at 0 and executes instructions" is a funny, but mostly true way to express this. Some people are shocked that no magic happens before the instructions start.
- zerohp 4y agoThis is pretty old. There's quite a lot that happens before instructions start on modern CPUs. Just one small example: CPUs have many small SRAM arrays for micro-architecture features like branch predictors. Some of these need to be initialized after reset by a state machine that takes many cycles. I have even heard of a large chip that pushes initialization vectors through the scan chains so that all flops begin in an initial state, without requiring a reset network.
- ip26 4y agosidebar, have a question about an older comment of yours that can't be replied to. would you reach out via email (in profile)?
- analog31 4y agoIt's easy to overlook for those who program mostly on higher level systems. There was a recent HN thread that I think pointed to this article on what happens before main() in C programs: https://embeddedartistry.com/blog/2019/04/08/a-general-overview-of-what-happens-before-main/ https://embeddedartistry.com/blog/2019/04/08/a-general-overv... On microcontrollers, there are often some preliminaries that are programmed into nonvolatile settings of the hardware, such as the type of clock oscillator. On a microprocessor like the Z80, your circuit was supposed to ensure that things like the clock oscillator and power supplies were stable before releasing the RESET pin.
- raggi 4y agoAs long as things like embedded coprocessors (IME, TXT, PSP, etc) are kept out of view.
- monocasa 4y agoSort of. It's actually fairly common on larger cores (and particular, larger SoCs) for there to exist magic that happens before architectural reset vectors. https://www.bunniestudios.com/blog/?p=5127 https://www.bunniestudios.com/blog/?p=5127 > By pre-boot code, I’m not talking about the little ROM blob that gets run after reset to set up your peripherals so you can pull your bootloader from SD card or SSD. That part was a no-brainer to share. I’m talking about the code that gets run before the architecturally guaranteed “reset vector”. A number of software developers (and alarmingly, some security experts) believe that the life of a CPU begins at the reset vector. In fact, there’s often a significant body of code that gets executed on a CPU to set things up to meet the architectural guarantees of a hard reset – bringing all the registers to their reset state, tuning clock generators, gating peripherals, and so forth. Critically, chip makers heavily rely upon this pre-boot code to also patch all kinds of embarrassing silicon bugs, and to enforce binning rules.
- billti 4y agoAmongst the first sentences... > It may be thought of as what happens when a whole computer starts, since the CPU is the center of the computer and the place where the action begins. I thought that too. Last year I spent a while getting as low-level as I could and trying to understand how to write a boot loader, a kernel, learn about clocks and pins and interrupts, etc. I thought, "I know, I'll get a Raspberry Pi! That way even if I brick it I didn't waste too much money". Turns out the Raspberry Pi (and I'm guessing many other systems) are pretty confusing to understand at boot time. For one, it's the GPU that actually does the initial boot process, and much of that is hard to find good info on. (https://raspberrypi.stackexchange.com/questions/14862/why-does-the-raspberry-pis-gpu-control-the-first-stages-of-the-boot-process https://raspberrypi.stackexchange.com/questions/14862/why-do...) I spent many many hours reading various specs & docs and watching tons of low-level YouTube videos. Compared to software development higher up the stack (my usual area), I found the material surprisingly sparse and poor for the most part. (Maybe that's reflective of the size of the audience and the value in producing it).
- pabs3 4y agoThis keynote about hardware vs operating systems knowledge of hardware was enlightening: https://www.youtube.com/watch?v=36myc8wQhLo https://www.youtube.com/watch?v=36myc8wQhLo
- _448 4y ago> Turns out the Raspberry Pi (and I'm guessing many other systems) are pretty confusing to understand at boot time. That is because how ARM ecosystem functions. There is no standard way of integrating ARM CPU into a product as Arm, the company, just sells base IP and not the complete CPU. Every ARM licensee, from Qualcomm to Apple to Nvidia are free to design their own extensions and integrations into their SoC. There is no standard for this. This creates a lot of problems for writing a generic tutorial that you see in the x86 world.
- Dork1234 4y agoMight want to look at MicroPython. The ports have various init functions for various chips /system. It might not be a full OS, but it is pretty low level code you can compare to various other systems. https://github.com/micropython/micropython/tree/master/ports https://github.com/micropython/micropython/tree/master/ports
- broast 4y agoAmazing to see that tripod sites are still around.
- greenyoda 4y agoEven stranger: If you go to www.tripod.com, it redirects to https://www.tripod.lycos.com https://www.tripod.lycos.com. Going to https://www.lycos.com https://www.lycos.com, you can see that Lycos, one of several search engines that predated Google, is still around. Here's their about page: https://info.lycos.com/about/company-overview/ https://info.lycos.com/about/company-overview/
- makeworld 4y agoIt seems like a pretty decent search engine also.
- systematical 4y agoIt's the only reason I clicked on this.
- andirk 4y agoMine's still around altho it looks like I turned it from a The Simpsons fan page in to one sentence https://bartzone.tripod.com/ https://bartzone.tripod.com/ . And with allowing all scripts, it's >1,000 requests, >10MB of data. These ad networks on top of ad networks on the oldest IE-compliant code with it's `document.write` fighting it out for eyeballs since 1999. As Lycos' motto says: Battling it out to complete obsolescence and will never give an inch. Go iframe go!
- hackan 4y agoIs it me or the article seems incomplete? It kinda finishes for me after: > The following are the memory ranges you get with a 2-to-4 converter on an 8-bit address bus: And that's it. It looks truncated, or incomplete :thinking:
- charcircuit 4y agoI thought it started by executing microcode from ROM.
- martyvis 4y agoWhich is precisely what another of today's HN posts alludes to https://news.ycombinator.com/item?id=34329201 https://news.ycombinator.com/item?id=34329201
- valleyer 4y agoIt does, in the sense that executing any (regular, macro) code involves executing microcode. But no, there's not a separate phase during which only microcode is executed, if that's what you mean.
- Rimintil 4y ago> The memory chips respond by sending the contents of the selected memory cell over the data bus to the CPU. What does that ROM memory cell _physically look like_? How do we physically manipulate it to contain a 1 or a 0 (absence of something)?
- Gordonjcp 4y agoInternally? Imagine a grid of wires where each address is one vertical wire and each bit of the output is one horizontal wire. The output wires have resistors pulling them up to 5V. To select an entry in the ROM you pull its corresponding vertical wire to ground. Now here's the clever bit - there are diodes between the vertical and horizontal wires. When you pull a vertical wire to ground it pulls all the horizontal wires connected through diodes to ground, putting a 0 on those pins. In a real "mask programmmed" ROM the grid is more square, so there are a lot of horizontal lines grouped in 8 bit bytes. In an EPROM the diode is replaced by a little MOSFET. By applying a high voltage to its gate it'll stay charged basically forever, switching on and forming a "0" in the output.
- convolvatron 4y agomy understanding is that there is a thin trace (a fuse) at each cell. in order to program it, the address lines are manipulated to select the word, and a programming voltage is applied (for some reason I remember 18v, but it really could be anything), that draws a large current across the fused and blows it. on a die, you wouldn't go through that trouble, you would just directly synthesize the zeros and ones. but we don't really use ROMs that much anymore, they are usually persistent and programmable
- wittenbunk 4y agoMany modern microcontrollers have programmable fuses for security reasons.
- wiml 4y agoEach type of memory has a somewhat different design, but generally, the address lines will control a pair of demultiplexers, one which activates a single row in a rectangular grid of memory cells, and one which reads a single column. (Old DRAM chips had separate RAS and CAS — row address select and column address select — phases.) Each memory cell in that row puts its value onto its column line, and the column portion of the address determines which column line is routed to the output pin and fed back to the data bus. Multiply everything by 16 for a 16-bit memory bus. The memory cell itself might be a handful of transistors forming a bistable flipflop (for SRAM), or it might be a capacitor and transistor (for DRAM), or a floating gate and transistor (for EPROM), or just a wire and transistor (for mask-ROM).
- deleted 4y ago[deleted]
- atomjames 4y agothe nand2tetris course is a nice primer for understanding this kind of stuff: nand2tetris.org/
- santadakota 4y agoBen Eater's fantastic video series on building a breadboard 6502 based computer and an 8-bit breadboard computer from scratch might be appreciated in this thread. 6502 playlist: https://www.youtube.com/watch?v=LnzuMJLZRdU&list=PLowKtXNTBypFbtuVMUVXNR0z1mu7dp7eH https://www.youtube.com/watch?v=LnzuMJLZRdU&list=PLowKtXNTBy... 8-bit build playlist: https://www.youtube.com/watch?v=HyznrdDSSGM&list=PLowKtXNTBypGqImE405J2565dvjafglHU https://www.youtube.com/watch?v=HyznrdDSSGM&list=PLowKtXNTBy... He also sells kits if one is interested in playing along.
- AceJohnny2 4y agoHighly recommend Ben Eater's video, which in this embedded developer's eyes has been the clearest, best explanation of the fundamentals of a CPU as I've ever seen.
- snvzz 4y agoSimilarly, I have come to appreciate rehsd's[0] efforts in building a 80286 computer. 0. https://www.youtube.com/@rehsd/videos https://www.youtube.com/@rehsd/videos
- rep_lodsb 4y agoWow, that series looks fascinating! Only watched the first video yet, after initializing itself the CPU actually runs this code (because D8-D15 is wired to zero): addr opcode FFFFF0 90 NOP FFFFF1 00 90 00 90 ADD [BX+SI+9000],DL FFFFF5 00 90 00 90 ADD [BX+SI+9000],DL FFFFF9 00 90 00 90 ADD [BX+SI+9000],DL FFFFFD 00 90 00 -- !! general protection fault You can see it read and write the same address three times, then fetch the interrupt 0Dh vector and push flags+CS+IP to the stack :)
- kens 4y agoIf anyone is interested in what happens with an older CPU, I've written up how the IBM 1401 from 1959 starts up: https://www.righto.com/2021/02/an-ibm-1401-mainframe-computer-at.html https://www.righto.com/2021/02/an-ibm-1401-mainframe-compute... Among other things, since it uses magnetic core memory, you can run the program that was loaded when you shut it off.
- TedDoesntTalk 4y agoGo Ken!
- fzliu 4y ago> This is because when the power supply is first powering up, even if it only takes a second or two, the CPU has already received "dirty" power, because the power supply was building up a steady stream of electricity. Digital logic chips like CPUs require precise voltages, and they get confused if they receive something outside their intended voltage range. This is only partially true. When digital chips boot up, gate outputs are in an indeterminate state. The reset sets them to know initial (and valid) values/bits.
- martyvis 4y agoAll so called digital devices are really analog devices corralled into operating using binary logic. All it takes is a volt or two applied or removed unexpectedly on those discrete components and you have a bit-flip and possible ensuing mayhem.
- squokko 4y agoNow there's a domain I haven't seen in a very long time.
- ChrisMarshallNY 4y agoLooks like old 8-bit computers. I remember this from my days of Machine Code, and that was a long time ago. Wonder when this was written? I would guess mid-1980s; maybe earlier. Back then, we were all a lot closer to the hardware.
- snvzz 4y agoA tangent, but I thought worth mentioning: If you like this sort of plain text technical document, you might enjoy browsing the net with Gopher. I recommend Gopherus[0] as a modern implementation that's cross-platform. 0. https://gopherus.sourceforge.net/ https://gopherus.sourceforge.net/
- sanatgersappa 4y agoHonestly, I had no idea tripod was still around.
- Wolfenstein98k 4y agoWhat a delightful article to read. Thanks for sharing!
- saagarjha 4y ago> The Z80's system, although simpler, creates a "hole" in the memory, because the bottom of the memory space is used by ROM and therefore you cannot use the beginning of the memory space for normal RAM work. Gameboy actually does a funny thing where the boot ROM gets mapped at the bottom of the address space, and then it writes to a MMIO address to unmap the ROM overlay and restore the first 256 bytes of the cartridge there instead. It’s quite amusing! > On some computer platforms, the instruction pointer is called the "program counter", inexplicably abbreviated "PG" Typo, maybe? Typically it’s called “pc”.
- Gordonjcp 4y agoCP/M systems used to do that too, where the ROM would copy its important bits to upper memory and then swap itself out.
- DotaFan 4y agoLast week I've tried to understand how Chip8 worked, and it did help me understand this article a bit more.
- dirtyid 4y agoSomewhere out there is a company specializing in selling tripods patiently waiting for the domain to free up.
- bandrami 4y agoTripod still exists?
- ruslan 4y agoStarting procedure on MOS6502 is not that simple as it is told in the article. It spends some 7 clocks on doing internal initialization and only then fetches address of first jump from reset vector (0xFFFC/0xFFFD). I find Ben Eater's series on building simple 8-bit breadboard computer using 6502 CPU very educating and entertaining. https://www.youtube.com/watch?v=HyznrdDSSGM https://www.youtube.com/watch?v=HyznrdDSSGM
- als0 4y ago> Regardless of where the CPU begins getting its instructions, the beginning point should always be somewhere in a ROM chip. The computer needs startup instructions to perform basic hardware checking and preparation, and these are contained in a ROM chip on the motherboard called the BIOS. This is where any computer begins executing its code when it is turned on. I can't see any date on this, but this is a bit antiquated. For security and reliability, modern CPUs have an on-chip ROM, which is executed first. That on-chip ROM will tend do basic things like check clock, power, memory etc. Once that's complete it will then securely load firmware from the motherboard flash. Even modern cheapo microcontrollers are shipping with on-chip ROM these days.