5 ms·

Learning Verilog and FPGA

95 points by bajsejohannes 4y ago

carlosedp 4y ago
I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better. I chose Chisel (https://www.chisel-lang.org/ https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation. I'd highly advise looking into it although also knowing Verilog helps a lot.
zwieback 4y ago
In the past I worked on a project with a soft CPU (Altera NIOS) with some custom Verilog written for glue logic. It was nice because the NIOS is just like a generic microcontroller so it's painless to try out some different Verilog blocks without having to interface an external micro. The toolchain is monstrous though, although free versions are available it's just a huge clunker to work with.
yummypaint 4y ago
For me the key to making everything understandable was adding more constraints to keep myself out of trouble. Everything is a finite state machine, exclusively non-blocking assignments, always loops use the rising edge of the clock signal only.
- JoachimS 4y ago
  Another strategy to make life easier is to separate data flow (the transformation of inputs to outputs) and control flows. The control flow knows the context, and given the current state decides how the data flow transformation is performed. Think of an ALU that can perform add, sub, shift operations. The ALU implementation simply accepts operands and perform one of the supported operations to generate the output. The control flow would in this case look at an opcode and decide which of the ALU operations to perform.
- JoachimS 4y ago
  I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS in a statement has been updated. IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end. https://github.com/secworks/prince/blob/master/src/rtl/prince_core.v https://github.com/secworks/prince/blob/master/src/rtl/princ... (Yes, I should really move the functions to a separate include file.) The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
bfrog 4y ago
I tried Verilog at first but found myself liking vhdl quite a lot more. It just fit my mental model better and helped avoid some really silly errors I kept making as a beginner. I could probably pick up Verilog now a bit quicker, I’d jump straight to system Verilog though if I did.
- bajsejohannes 4y ago
  Verilog does make it fantastically easy to create bugs! It feels like very early C versions that are way too lenient. The biggest bang-for-the-buck you can get here is adding "`default_nettype none" at the top of every file, which makes undeclared identifiers an error. I believe this is SystemVerilog, though, and I agree that's what you should learn.
  - _0ffh 4y ago
    The default_nettype directive is at least in the Verilog 2001 standard. Ed. Seems it's in Verilog-1995, too: http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_ref_top.html http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_r...
- fayalalebrun 4y ago
  You should try out Chisel. I learned and used VHDL first, but after switching to Chisel I realized it was much better designed and avoided many of the footguns you'll likely encounter with Verilog or VHDL. And in general, it is a joy to work with.
  - bfrog 4y ago
    I like the idea of a newer language but inevitably it feels like anything not Verilog or vhdl is missing direct tooling support from the vendors. Do any vendors intend on supporting chisel? Does chisel have enough control to ensure generated vhdl/Verilog match the what vendors look for to infer certain things like certain ram and dsp instances? Does chisel have a fast simulator like ghdl?
steponlego 4y ago
Is there an FPGA with a totally Free and Open toolkit yet?
- tieze 4y ago
  Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis https://github.com/YosysHQ/prjtrellis Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use. In general the hardware toolchains feel very ancient compared to software toolchains.
  - robinsonb5 4y ago
    Yosys / project Trellis and nextpnr are amazing - I've played with them using an IceSugar-Pro board (which despite its name has an ECP5-25 FPGA) - but there's also an experimental branch for Xilinx 7-series devices now - Project X-ray, with an even more experimental branch of that targetting the Kintex7-325 FPGA on one of the QMTech (AliExpress) boards. That's of particular interest since that FPGA is large / high-end enough not to be supported by the free version of Vivado!
- waste_monk 4y ago
  I believe there's a foss toolchain for the Lattice ice40 series (?)
- ghostDancer 4y ago
  Not sure how many boards supported but you can take a look to Icestudio https://icestudio.io/ https://icestudio.io/
- goku12 4y ago
  QuickLogic [1] seems to support and target the open tool environment for their devices -especially the F4PGA [2] toolkit (known earlier as symbiflow). Others have mentioned Lattice FPGAs. But the impression I got from Lattice is that they like the development of open tools, but don't want to invest too much in it. QuickLogic on the other hand, contribute code and design directly to F4PGA project and allied ones like Migen. [1]: https://www.quicklogic.com/software/qorc-mcu-efpga-fpga-open-source-tools/ https://www.quicklogic.com/software/qorc-mcu-efpga-fpga-open... [2]: https://f4pga.org/ https://f4pga.org/
chunsj 4y ago
In my case, building a miner and computation accelerator with FPGA boards really help me understanding the applications of FPGA. Though I have started learning HDL languages to build digital circuits, to me, that' not such an interesting subject, however, accelerated computing with FPGA had been very interesting experience.
- eachro 4y ago
  What are the sort of applications that FPGAs enable/accelerate?
  - le-mark 4y ago
    Seems like fpga are more for hardware designs that need more compute than a DSP can provide. It’s nearly impossible to beat modern GPUs for compute power, but they also can’t or aren’t be integrated into a board that controls a microwave transponder, radar, or whatever. I’m a laymen though, hopefully someone will correct this post.
    - bajsejohannes 4y ago
      I think the answer is that it depends on what exactly you're optimizing for and what the workload is. I no expert either, but some of my predictions would be: DSPs and FPGAs will be great at compute per watt. FPGAs will have the highest initial cost. GPUs might beat FPGAs on floating point performance.
alexarnesen 4y ago
Greg Stitt shares amazing training materials freely (he uses them for his undergraduate and graduate courses). His synthesizable HDL methods are really empowering for beginner developers https://github.com/ARC-Lab-UF/vhdl-tutorial https://github.com/ARC-Lab-UF/vhdl-tutorial http://www.gstitt.ece.ufl.edu/ http://www.gstitt.ece.ufl.edu/

95 points by bajsejohannes 4y ago

I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better. I chose Chisel (https://www.chisel-lang.org/ https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation. I'd highly advise looking into it although also knowing Verilog helps a lot.

zwieback 4y ago

In the past I worked on a project with a soft CPU (Altera NIOS) with some custom Verilog written for glue logic. It was nice because the NIOS is just like a generic microcontroller so it's painless to try out some different Verilog blocks without having to interface an external micro. The toolchain is monstrous though, although free versions are available it's just a huge clunker to work with.

yummypaint 4y ago

For me the key to making everything understandable was adding more constraints to keep myself out of trouble. Everything is a finite state machine, exclusively non-blocking assignments, always loops use the rising edge of the clock signal only.

JoachimS 4y ago
Another strategy to make life easier is to separate data flow (the transformation of inputs to outputs) and control flows. The control flow knows the context, and given the current state decides how the data flow transformation is performed. Think of an ALU that can perform add, sub, shift operations. The ALU implementation simply accepts operands and perform one of the supported operations to generate the output. The control flow would in this case look at an opcode and decide which of the ALU operations to perform.
JoachimS 4y ago
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS in a statement has been updated. IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end. https://github.com/secworks/prince/blob/master/src/rtl/prince_core.v https://github.com/secworks/prince/blob/master/src/rtl/princ... (Yes, I should really move the functions to a separate include file.) The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.

bfrog 4y ago

I tried Verilog at first but found myself liking vhdl quite a lot more. It just fit my mental model better and helped avoid some really silly errors I kept making as a beginner. I could probably pick up Verilog now a bit quicker, I’d jump straight to system Verilog though if I did.

bajsejohannes 4y ago
Verilog does make it fantastically easy to create bugs! It feels like very early C versions that are way too lenient. The biggest bang-for-the-buck you can get here is adding "`default_nettype none" at the top of every file, which makes undeclared identifiers an error. I believe this is SystemVerilog, though, and I agree that's what you should learn.
- _0ffh 4y ago
  The default_nettype directive is at least in the Verilog 2001 standard. Ed. Seems it's in Verilog-1995, too: http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_ref_top.html http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_r...
fayalalebrun 4y ago
You should try out Chisel. I learned and used VHDL first, but after switching to Chisel I realized it was much better designed and avoided many of the footguns you'll likely encounter with Verilog or VHDL. And in general, it is a joy to work with.
- bfrog 4y ago
  I like the idea of a newer language but inevitably it feels like anything not Verilog or vhdl is missing direct tooling support from the vendors. Do any vendors intend on supporting chisel? Does chisel have enough control to ensure generated vhdl/Verilog match the what vendors look for to infer certain things like certain ram and dsp instances? Does chisel have a fast simulator like ghdl?

steponlego 4y ago

Is there an FPGA with a totally Free and Open toolkit yet?

tieze 4y ago
Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis https://github.com/YosysHQ/prjtrellis Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use. In general the hardware toolchains feel very ancient compared to software toolchains.
- robinsonb5 4y ago
  Yosys / project Trellis and nextpnr are amazing - I've played with them using an IceSugar-Pro board (which despite its name has an ECP5-25 FPGA) - but there's also an experimental branch for Xilinx 7-series devices now - Project X-ray, with an even more experimental branch of that targetting the Kintex7-325 FPGA on one of the QMTech (AliExpress) boards. That's of particular interest since that FPGA is large / high-end enough not to be supported by the free version of Vivado!
waste_monk 4y ago
I believe there's a foss toolchain for the Lattice ice40 series (?)
ghostDancer 4y ago
Not sure how many boards supported but you can take a look to Icestudio https://icestudio.io/ https://icestudio.io/
goku12 4y ago
QuickLogic [1] seems to support and target the open tool environment for their devices -especially the F4PGA [2] toolkit (known earlier as symbiflow). Others have mentioned Lattice FPGAs. But the impression I got from Lattice is that they like the development of open tools, but don't want to invest too much in it. QuickLogic on the other hand, contribute code and design directly to F4PGA project and allied ones like Migen. [1]: https://www.quicklogic.com/software/qorc-mcu-efpga-fpga-open-source-tools/ https://www.quicklogic.com/software/qorc-mcu-efpga-fpga-open... [2]: https://f4pga.org/ https://f4pga.org/

chunsj 4y ago

In my case, building a miner and computation accelerator with FPGA boards really help me understanding the applications of FPGA. Though I have started learning HDL languages to build digital circuits, to me, that' not such an interesting subject, however, accelerated computing with FPGA had been very interesting experience.

eachro 4y ago
What are the sort of applications that FPGAs enable/accelerate?
- le-mark 4y ago
  Seems like fpga are more for hardware designs that need more compute than a DSP can provide. It’s nearly impossible to beat modern GPUs for compute power, but they also can’t or aren’t be integrated into a board that controls a microwave transponder, radar, or whatever. I’m a laymen though, hopefully someone will correct this post.
  - bajsejohannes 4y ago
    I think the answer is that it depends on what exactly you're optimizing for and what the workload is. I no expert either, but some of my predictions would be: DSPs and FPGAs will be great at compute per watt. FPGAs will have the highest initial cost. GPUs might beat FPGAs on floating point performance.

alexarnesen 4y ago

Greg Stitt shares amazing training materials freely (he uses them for his undergraduate and graduate courses). His synthesizable HDL methods are really empowering for beginner developers https://github.com/ARC-Lab-UF/vhdl-tutorial https://github.com/ARC-Lab-UF/vhdl-tutorial http://www.gstitt.ece.ufl.edu/ http://www.gstitt.ece.ufl.edu/