4 ms·

From a signal integrity standpoint, you really don't want both pins (i.e. SSRX1 and SSRX2) tied together. A lot of USB3 routing is reducing stubs. When the sig

From a signal integrity standpoint, you really don't want both pins (i.e. SSRX1 and SSRX2) tied together. A lot of USB3 routing is reducing stubs. When the signals are going as fast as they are in USB3, they're essentially a wave going down the line, and if there's a "stub" the wave will actually hit the end of the wire and reflect back, causing interference. Having one of the pins not connect to your processor would create a stub inherent in the design, which is probably a bad idea. When you dig into the details of the signals of USB3+ electrically it's truly remarkable they're able to mass produce cheap consumer grade equipment to implement it. To give you an idea, the lengths of USB3 traces in your board need to be matched, so you add wiggles to the shorter trace to make it ever so slightly longer. But those wiggles can't get too far from the opposing trace in the diff pair either because that changes the way the traces are coupled together. Also, if the layer above/below is not a solid ground plane, you will run into issues as the signal will propagate through the wire faster/slower depending on what's around it. This is so critical that you use "impedance controlled" PCBs that place a tight tolerance on the spacing of your layers so that you can be sure it doesn't change along the length of your trace. And, of course, you want to avoid sharp bends in your traces as those will act like a stub. None of this is bad engineering on the part of the USB IF, just that if you want to send data over a USB cable reliably at 5gbits, or now 40gbits, you're really pushing the limits of modern electrical design.

xg15 4y ago
> From a signal integrity standpoint, you really don't want both pins (i.e. SSRX1 and SSRX2) tied together. > Having one of the pins not connect to your processor would create a stub inherent in the design, which is probably a bad idea. I was more thinking that each wire for a lane has two pins, one on the top and one on the bottom, which are electrically connected. So e.g. SSRX1+ on the top would be connected to SSRX1+ on the bottom, SSRX1- on the top with SSRX1- on the bottom, same for SSRX2+, -, etc. With the same wiring in the plug as well as in the socket, there wouldn't be any disconnected pins. The wire for e.g. SSRX1+ would split before the plug, then lead to two pins in the plug; the plug connects to two matching pins in the socket which merge back into a single wire. So in that modified header one differential pair would occupy four pins, two in the top row and two in the mirrored bottom row. This means the header would have 4 additional pins per row (so 8 in total) compared to what it has now. But of course the splits and merges in the wire might cause interference as well.
- klysm 4y ago
  The signal reflections from the stub can propagate all the way back to the source. This means you’d have to use two transmitters to avoid interference from those reflections.
  - function_seven 4y ago
    If there’s only one wire in the cable, and one trace leading up to the socket, would there still be a stub? Have the sockets pins both tied to the same trace, and have the plug terminals both tie to the same wire.
- Denvercoder9 4y ago
  I'm not an expert; but having splits and merges in your traces and wires when you need to have matched signal path length seems like a terrible idea.
- exmadscientist 4y ago
  The four additional pins are a nontrivial problem. The Type-C connector is already annoyingly large as is. The stubs others have talked about are a major problem; they're really hard to avoid. In fact, they're so hard to deal with, that a lot of effort in routing goes to keeping things in the right order on the board. By that I mean that when you leave, say, your upstream device and run the traces to downstream, you need to have them come out in the same order: if you start with _P on the left and _N on the right, you want to end that way. A swapover is annoying at USB 2 480Mbps speeds and utterly awful at 20Gbps. (There is also a >50% chance that you miswired the thing and are wiring _P to _N, which increases to >99% if the routing came out naturally neat, but that's just Murphy's Law in action.) It's so difficult and awful to deal with this stuff that USB 3 took a page from Gigabit Ethernet and usually features transceivers that just figure it out: they know you have eight wires in four pairs between eight pins and they can work with that. Once you have that feature, and transceivers definitely do, there is no point whatsoever in trying to make superfluous changes at the connector bit.
- paulywog 4y ago
  The splits and merges would definitely affect signal integrity. Signal integrity is one of those fields that can feel like dark voodoo magic. I know people who are signal integrity experts by trade. Would the splits and merges definitely make the signal integrity worse to the point that it wouldn't work? Maybe not. But if you're designing a high speed cutting edge standard, you probably don't want to make decisions that limit the best signal integrity an implementer could achieve. Signal integrity is all about balancing the bad SI decisions you have to make because of some product goal or whatever with tighter tolerances elsewhere. The more "clean" the standard is, the more tolerance it has for the implementers.
chis 4y ago
Amazing comment. Where did you learn about this?
- rolenthedeep 4y ago
  This is all pretty standard electronics design these days. If you're interested to learn more, you can search for "differential signaling". What it comes down to is that once your signal rate is high enough, the speed that electrons move becomes a concern. Matching the length of your traces ensures that a signal sent down two wires at the same time arrives at the same time. That's the general idea anyway. This topic gets very complex the further down you go
  - mlyle 4y ago
    > What it comes down to is that once your signal rate is high enough, the speed that electrons move becomes a concern. To be clear-- the speed that charge moves in the cable. The actual electrons move really, really slow-- often centimeters per hour slow.
    - rolenthedeep 4y ago
      While that's true, it sounds much less exciting.
- amelius 4y ago
  It's basic transmission line theory. https://en.wikipedia.org/wiki/Transmission_line https://en.wikipedia.org/wiki/Transmission_line
- paulywog 4y ago
  The other commenters got it spot on for where you can learn more, but as to where I learned it, I decided I wanted to build a project with USB C running at 3.0 speeds and had to deep dive on the subject in order to make it work. It was surprisingly hard to gather all of this information in one place and actually implement it given the resources on the internet a few years ago. Even then, there were still some board revisions that got it a bit wrong, one where I left out the decoupling capacitors I'd later learn were a critical detail, and one where I put all the wiggles clumped together at the middle of the shorter trace and so despite both signals arriving at the end at the correct time, they were out of phase for nearly the whole trace run and caused (presumably) cross talk between each other. But I did get it working in the end :)

xg15 4y ago

> From a signal integrity standpoint, you really don't want both pins (i.e. SSRX1 and SSRX2) tied together. > Having one of the pins not connect to your processor would create a stub inherent in the design, which is probably a bad idea. I was more thinking that each wire for a lane has two pins, one on the top and one on the bottom, which are electrically connected. So e.g. SSRX1+ on the top would be connected to SSRX1+ on the bottom, SSRX1- on the top with SSRX1- on the bottom, same for SSRX2+, -, etc. With the same wiring in the plug as well as in the socket, there wouldn't be any disconnected pins. The wire for e.g. SSRX1+ would split before the plug, then lead to two pins in the plug; the plug connects to two matching pins in the socket which merge back into a single wire. So in that modified header one differential pair would occupy four pins, two in the top row and two in the mirrored bottom row. This means the header would have 4 additional pins per row (so 8 in total) compared to what it has now. But of course the splits and merges in the wire might cause interference as well.

klysm 4y ago
The signal reflections from the stub can propagate all the way back to the source. This means you’d have to use two transmitters to avoid interference from those reflections.
- function_seven 4y ago
  If there’s only one wire in the cable, and one trace leading up to the socket, would there still be a stub? Have the sockets pins both tied to the same trace, and have the plug terminals both tie to the same wire.
Denvercoder9 4y ago
I'm not an expert; but having splits and merges in your traces and wires when you need to have matched signal path length seems like a terrible idea.
exmadscientist 4y ago
The four additional pins are a nontrivial problem. The Type-C connector is already annoyingly large as is. The stubs others have talked about are a major problem; they're really hard to avoid. In fact, they're so hard to deal with, that a lot of effort in routing goes to keeping things in the right order on the board. By that I mean that when you leave, say, your upstream device and run the traces to downstream, you need to have them come out in the same order: if you start with _P on the left and _N on the right, you want to end that way. A swapover is annoying at USB 2 480Mbps speeds and utterly awful at 20Gbps. (There is also a >50% chance that you miswired the thing and are wiring _P to _N, which increases to >99% if the routing came out naturally neat, but that's just Murphy's Law in action.) It's so difficult and awful to deal with this stuff that USB 3 took a page from Gigabit Ethernet and usually features transceivers that just figure it out: they know you have eight wires in four pairs between eight pins and they can work with that. Once you have that feature, and transceivers definitely do, there is no point whatsoever in trying to make superfluous changes at the connector bit.
paulywog 4y ago
The splits and merges would definitely affect signal integrity. Signal integrity is one of those fields that can feel like dark voodoo magic. I know people who are signal integrity experts by trade. Would the splits and merges definitely make the signal integrity worse to the point that it wouldn't work? Maybe not. But if you're designing a high speed cutting edge standard, you probably don't want to make decisions that limit the best signal integrity an implementer could achieve. Signal integrity is all about balancing the bad SI decisions you have to make because of some product goal or whatever with tighter tolerances elsewhere. The more "clean" the standard is, the more tolerance it has for the implementers.

chis 4y ago

Amazing comment. Where did you learn about this?

rolenthedeep 4y ago
This is all pretty standard electronics design these days. If you're interested to learn more, you can search for "differential signaling". What it comes down to is that once your signal rate is high enough, the speed that electrons move becomes a concern. Matching the length of your traces ensures that a signal sent down two wires at the same time arrives at the same time. That's the general idea anyway. This topic gets very complex the further down you go
- mlyle 4y ago
  > What it comes down to is that once your signal rate is high enough, the speed that electrons move becomes a concern. To be clear-- the speed that charge moves in the cable. The actual electrons move really, really slow-- often centimeters per hour slow.
  - rolenthedeep 4y ago
    While that's true, it sounds much less exciting.
amelius 4y ago
It's basic transmission line theory. https://en.wikipedia.org/wiki/Transmission_line https://en.wikipedia.org/wiki/Transmission_line
paulywog 4y ago
The other commenters got it spot on for where you can learn more, but as to where I learned it, I decided I wanted to build a project with USB C running at 3.0 speeds and had to deep dive on the subject in order to make it work. It was surprisingly hard to gather all of this information in one place and actually implement it given the resources on the internet a few years ago. Even then, there were still some board revisions that got it a bit wrong, one where I left out the decoupling capacitors I'd later learn were a critical detail, and one where I put all the wiggles clumped together at the middle of the shorter trace and so despite both signals arriving at the end at the correct time, they were out of phase for nearly the whole trace run and caused (presumably) cross talk between each other. But I did get it working in the end :)