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Vector instructions (ala Cray) are future proof in ways that SIMD are not. Eventually every high performance CPU will have HBM, I am not sure SIMD is the mechan

Vector instructions (ala Cray) are future proof in ways that SIMD are not. Eventually every high performance CPU will have HBM, I am not sure SIMD is the mechanism we will use in to extract the most efficiency out of the platform. https://people.eecs.berkeley.edu/~krste/papers/yunsup-ms.pdf https://people.eecs.berkeley.edu/~krste/papers/yunsup-ms.pdf https://parlab.eecs.berkeley.edu/sites/all/parlab/files/maven-poster-parlab2009-06-01.pdf https://parlab.eecs.berkeley.edu/sites/all/parlab/files/mave... https://www.cs.uic.edu/~ajayk/c566/VectorProcessors.pdf https://www.cs.uic.edu/~ajayk/c566/VectorProcessors.pdf https://inst.eecs.berkeley.edu/~cs152/sp18/lectures/L16-RISCV-Vectors.pdf https://inst.eecs.berkeley.edu/~cs152/sp18/lectures/L16-RISC...

janwas 4y ago
I feel that SIMD vs vector is not the most useful distinction to make. Yes, at the ISA and binutils level there is a difference in terms of number of instructions and ugly encodings. But the actual application source code can actually look the same for SIMD and vector - vector-length agnostic style is helpful for both. Instead, it seems more interesting to focus on preparing more applications for either SIMD or vector: with data-parallel algorithms, avoiding branches etc.
lifthrasiir 4y ago
Of course when you only have packed instructions (a la SIMD) you have no choice but using them in place of vector instructions, but vector instructions in general do not fully subsume packed instructions. I think packed instructions are better at exploiting opportunistic parallelism from either a short loop (where vector instructions would have higher overhead) or a series of similar but slightly different scalar instructions.
fooblaster 4y ago
There have been attempts to remedy the fixed width simd vector problem that are already shipping: https://developer.arm.com/Architectures/Scalable%20Vector%20Extensions https://developer.arm.com/Architectures/Scalable%20Vector%20...

janwas 4y ago

I feel that SIMD vs vector is not the most useful distinction to make. Yes, at the ISA and binutils level there is a difference in terms of number of instructions and ugly encodings. But the actual application source code can actually look the same for SIMD and vector - vector-length agnostic style is helpful for both. Instead, it seems more interesting to focus on preparing more applications for either SIMD or vector: with data-parallel algorithms, avoiding branches etc.

lifthrasiir 4y ago

Of course when you only have packed instructions (a la SIMD) you have no choice but using them in place of vector instructions, but vector instructions in general do not fully subsume packed instructions. I think packed instructions are better at exploiting opportunistic parallelism from either a short loop (where vector instructions would have higher overhead) or a series of similar but slightly different scalar instructions.

fooblaster 4y ago

There have been attempts to remedy the fixed width simd vector problem that are already shipping: https://developer.arm.com/Architectures/Scalable%20Vector%20Extensions https://developer.arm.com/Architectures/Scalable%20Vector%20...