3 ms·
> It now feels like the real benefit that A64 ISA has is the fact that the instructions are all 4 bytes in size, which makes it much easier to implement wide fr
by api 4y ago
> It now feels like the real benefit that A64 ISA has is the fact that the instructions are all 4 bytes in size, which makes it much easier to implement wide frontends4 - coincidentally this of course seems to be where all the irregularities come from, as you effectively need to devise an encoding that makes it possible to unambiguously encode a large set of instructions and as much data as possible in some of them.
That's not pragmatism per se. It's purity, but optimizing for something else: wide front ends and dense code to minimize memory overhead. Those are the right things to optimize for on a modern chip.
Somewhat complicated decodes are fine as long as you don't have to do crazy things to guess the width of instructions like you do on x64.
- zozbot234 4y agoEven with something as clean as RISC-V, you still need a serial computation to determine insn boundaries. Yes it's a whole lot cleaner than x86-64, but in principle very wide insn decode might still be affected.
- snvzz 4y agoRISC-V instruction length is in the first two bits of every instruction; 3 of 4 values mean the instruction is 16-bit, the remaining value is for 32-bit. The complexity this adds to decode is a far cry from the brute-force approach x86 requires. This negligible impact is weighted against the benefits of higher code density; RISC-V is the most dense ISA, for 32 and 64 bit. ARM's AARCH64 does in contrast have exceptionally poor code density for a 64bit architecture. This translates in much higher requirements for cache sizes and ROM size, which in turn mean larger area and higher power consumption for a given performance target.