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Largely agree with you here but I think there were two other factors in RISC's early success: 1. As microprocessors became dominant freezing complex microcode

Largely agree with you here but I think there were two other factors in RISC's early success: 1. As microprocessors became dominant freezing complex microcode - with possible bugs - on an IC was a really bad idea. Better to run with simpler instructions and less microcode. Look at the debugging issues that National Semiconductor had with the NS32016 - which I think really hindered its adoption. 2. You needed a much smaller team to design a RISC CPU - low double figures for IBM 801, Berkeley RISC, MIPS and Arm. This opened the door to lots of experiments and business models that would not have been possible with CISC.

_0ffh 4y ago
Yep, RISC is really a KISS CPU, paired with the attempt to draw the maximal advantage from the potential strengths of the underlying concept. And it turned out pretty nicely imho.
sitkack 4y ago
Almost no systems use fixed microcode. What RISC took advantage of was decoupling the memory bus from the CPU clock rate and the introduction of instruction and data caches. RISC is a simple interface, but the internal processor complexity is as high or higher than CISC (thanks to RISC simplicity). Speculative execution, reordering instructions, hazards, branch prediction these issues are the same across both. The front end isn't this huge deal. CPUs all do the same thing, attempt to unroll huge state machines and compress time. The ISA is just a way to get that problem into the CPU.
- klelatti 4y ago
  The key word in my comment is ‘early’. You’re right about architectures today but that explicitly wasn’t what I was talking about. Caches we’re important in the IBM 801 but your orher points don’t apply to early RISC designs.
  - sitkack 4y ago
    RISC didn't hit its stride until the early 80s, using caches. The 801 was an experiment. When the 801 shipped, almost no system had hard coded microcode. Being able to update microcode in the field isn't the reason RISC thrived.
    - klelatti 4y ago
      I can think of at least two of the RISC pioneers who have cited buggy CISC architectures / microcode as a key motivating reason for adopting RISC. I actually cited an example of a major CISC design that basically failed because it was so buggy. The early microprocessors all had hard coded microcode - Intel only had upgradeable microcode with P6 in the mid 1990s. I didn't say that it was the reason - there were many reasons - but that it was one factor. It was absolutely the case that original RISC designs were simpler to design and that helped them to get traction. Edit - just to add that caches enabled RISC to get decent performance but they were not by themselves a reason for choosing RISC over CISC.
    - abiloe 4y ago
      > When the 801 shipped, almost no system had hard coded microcode. 1990? No system without soft microcode? That's a very restricted definition of system for the field of computing in 1990.
    - skissane 4y ago
      > When the 801 shipped, almost no system had hard coded microcode. Intel 8086 was introduced in 1978, with hardcoded microcode. Intel didn’t introduce microcode patching support until the Pentium Pro in 1995.
      - sitkack 4y ago
        Intel chips were not "systems", they were disposable microprocessors. Systems have updates and field support personnel. Lousy counterfactuals sleep furiously.
- deleted 4y ago
  [deleted]

_0ffh 4y ago

Yep, RISC is really a KISS CPU, paired with the attempt to draw the maximal advantage from the potential strengths of the underlying concept. And it turned out pretty nicely imho.

sitkack 4y ago

Almost no systems use fixed microcode. What RISC took advantage of was decoupling the memory bus from the CPU clock rate and the introduction of instruction and data caches. RISC is a simple interface, but the internal processor complexity is as high or higher than CISC (thanks to RISC simplicity). Speculative execution, reordering instructions, hazards, branch prediction these issues are the same across both. The front end isn't this huge deal. CPUs all do the same thing, attempt to unroll huge state machines and compress time. The ISA is just a way to get that problem into the CPU.

klelatti 4y ago
The key word in my comment is ‘early’. You’re right about architectures today but that explicitly wasn’t what I was talking about. Caches we’re important in the IBM 801 but your orher points don’t apply to early RISC designs.
- sitkack 4y ago
  RISC didn't hit its stride until the early 80s, using caches. The 801 was an experiment. When the 801 shipped, almost no system had hard coded microcode. Being able to update microcode in the field isn't the reason RISC thrived.
  - klelatti 4y ago
    I can think of at least two of the RISC pioneers who have cited buggy CISC architectures / microcode as a key motivating reason for adopting RISC. I actually cited an example of a major CISC design that basically failed because it was so buggy. The early microprocessors all had hard coded microcode - Intel only had upgradeable microcode with P6 in the mid 1990s. I didn't say that it was the reason - there were many reasons - but that it was one factor. It was absolutely the case that original RISC designs were simpler to design and that helped them to get traction. Edit - just to add that caches enabled RISC to get decent performance but they were not by themselves a reason for choosing RISC over CISC.
  - abiloe 4y ago
    > When the 801 shipped, almost no system had hard coded microcode. 1990? No system without soft microcode? That's a very restricted definition of system for the field of computing in 1990.
  - skissane 4y ago
    > When the 801 shipped, almost no system had hard coded microcode. Intel 8086 was introduced in 1978, with hardcoded microcode. Intel didn’t introduce microcode patching support until the Pentium Pro in 1995.
    - sitkack 4y ago
      Intel chips were not "systems", they were disposable microprocessors. Systems have updates and field support personnel. Lousy counterfactuals sleep furiously.
deleted 4y ago
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