3 ms·

Note that these extensions are primarily aimed at tiny embedded systems with code in ROM and no caches, so instruction fetch competing with data load/store is a

Note that these extensions are primarily aimed at tiny embedded systems with code in ROM and no caches, so instruction fetch competing with data load/store is an issue. That was the major justification for load/store multiple in the 1985 ARM ISA, but it's been dropped or deprecated in recent ARM -A ISAs. Byte and half load/store are also a lot more common in embedded software than in applications processors (especially as they are often handled by SIMD/Vector in larger CPUs) Note that the B extension already added instructions such as manipulating single bits in registers (Zbs); clz, cpop, byte reverse, rotates (Zbb); and shift-and-add (Zba) The Zcmp and Zcmt extensions are NOT intended to be added to large applications processors running standard OSes such as Linux or Android. This is about competing with 8051, AVR, PIC, MSP430, ARMv6-M, ARMv7-M at the lowest end.

wyldfire 4y ago
> 1985 ARM ISA, but it's been dropped or deprecated in recent ARM -A ISAs I guess the idea is to recover the opcode space? Or recover the area used to implement it? Seems like deprecating instructions for an ISA doesn't really have any effect other than giving you more notice for the eventual removal. Unless you sit down and read the new PRM you'd probably never know.
- phire 4y ago
  ARMv8-A (aka 64bit ARM) is a completely different instruction set, with basically zero relation to the instruction encoding of 32bit ARM. They redesigned it from scratch. And it's an instruction set designed for high-performance application cores (hence the -A) like what you would find as the main processor of a mobile phone, or a laptop or even a server. So they don't want anything optimised for lower-end designs. Plenty of other useful things to do with the encoding space. For those low-end designs, ARM have a second ISA called ARMv8-M. Which is basically just the old thumb mode of 32bit arm with a few improvements. The original 32bit arm ISA is basically dead these days (at least for new designs). You can still run some ARMv8-A chips in 32bit ARM mode, for compatibility. But that's actually optional in regards to the spec. Some only support running usermode 32bit ARM code. In the near future, we will see some cores that don't support 32bit arm code at all.
  - brucehoult 4y ago
    >In the near future, we will see some cores that don't support 32bit arm code at all. We already do. Lots of them. Every iPhone since the iPhone 8. M1 and M2 Macs. ThunderX in server farms, Cortex-X2 and Cortex-A510 cores in your high end 2022 Android phones (Galaxy S22, Xiaomi 12 etc). The Cortex-A710 cores in those phones do still run 32 bit code if needed. ARM has said all new applications processor cores from 2023 will drop 32 bit support.
    - hajile 4y ago
      X3 and A715 already dropped support (though maybe they're talking about shipped CPUs).
Dylan16807 4y ago
I feel like "NOT intended" is even understating it, so I'll quote your other post: "Code using Zcmp or Zcmt is incompatible with the RV64GC ISA assumed by current Linux etc OSes as it redefines and reuses the 16 bit opcodes for double precision floating point load and store. Full-size instructions must be used instead." I'm amused that the instructions that get the best compression by far, multi-register push/pop, are also the instructions that are too much of a pain to bother with on large cores.

wyldfire 4y ago

> 1985 ARM ISA, but it's been dropped or deprecated in recent ARM -A ISAs I guess the idea is to recover the opcode space? Or recover the area used to implement it? Seems like deprecating instructions for an ISA doesn't really have any effect other than giving you more notice for the eventual removal. Unless you sit down and read the new PRM you'd probably never know.

phire 4y ago
ARMv8-A (aka 64bit ARM) is a completely different instruction set, with basically zero relation to the instruction encoding of 32bit ARM. They redesigned it from scratch. And it's an instruction set designed for high-performance application cores (hence the -A) like what you would find as the main processor of a mobile phone, or a laptop or even a server. So they don't want anything optimised for lower-end designs. Plenty of other useful things to do with the encoding space. For those low-end designs, ARM have a second ISA called ARMv8-M. Which is basically just the old thumb mode of 32bit arm with a few improvements. The original 32bit arm ISA is basically dead these days (at least for new designs). You can still run some ARMv8-A chips in 32bit ARM mode, for compatibility. But that's actually optional in regards to the spec. Some only support running usermode 32bit ARM code. In the near future, we will see some cores that don't support 32bit arm code at all.
- brucehoult 4y ago
  >In the near future, we will see some cores that don't support 32bit arm code at all. We already do. Lots of them. Every iPhone since the iPhone 8. M1 and M2 Macs. ThunderX in server farms, Cortex-X2 and Cortex-A510 cores in your high end 2022 Android phones (Galaxy S22, Xiaomi 12 etc). The Cortex-A710 cores in those phones do still run 32 bit code if needed. ARM has said all new applications processor cores from 2023 will drop 32 bit support.
  - hajile 4y ago
    X3 and A715 already dropped support (though maybe they're talking about shipped CPUs).

Dylan16807 4y ago

I feel like "NOT intended" is even understating it, so I'll quote your other post: "Code using Zcmp or Zcmt is incompatible with the RV64GC ISA assumed by current Linux etc OSes as it redefines and reuses the 16 bit opcodes for double precision floating point load and store. Full-size instructions must be used instead." I'm amused that the instructions that get the best compression by far, multi-register push/pop, are also the instructions that are too much of a pain to bother with on large cores.