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I take your meaning, but just to nitpick one thing here in your argument: SystemVerilog is commonly used to model an abstract machine which is then synthesized

I take your meaning, but just to nitpick one thing here in your argument: SystemVerilog is commonly used to model an abstract machine which is then synthesized into realizable circuits. Its selling point was compatibility and similarity to C, Verilog, and VHDL, all textual languages because the proprietary processing code was built that way. It doesn’t necessarily have to be this way, but it turned out this way, so logic designers don’t have another realistic option. Combine this with the misconception that HDLs are programming instead of modeling, and you have a setup for confusion. https://research.ibm.com/haifa/Workshops/verification2004/papers/system_verilog_overview-ibm-symposium-johny_srouji.pdf https://research.ibm.com/haifa/Workshops/verification2004/pa...

IshKebab 4y ago
> It doesn’t necessarily have to be this way, but it turned out this way, so logic designers don’t have another realistic option. I mean, I think if graphical programming were really that compelling another option would have presented itself. People are constantly trying to introduce new graphical programming systems. > Combine this with the misconception that HDLs are programming instead of modeling I don't think that's really a misconception unless you have an especially pedantic definition of "programming". As you literally just said, Verilog was originally designed for simulation only - you literally were writing a simulation program. The act of programming Verilog is not really that different from programming C. The only difference is that the abstract machine your code runs in is very different (for synthesisable code anyway).