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Very nice to see RISC-V growing like that and being in the area of interest by big names such as Google and Intel. Open solutions are critical for risk manageme
by Reitet00 4y ago
Very nice to see RISC-V growing like that and being in the area of interest by big names such as Google and Intel. Open solutions are critical for risk management but I wonder if desktop/server RISC-V processors are also planned.
- ghaff 4y agoThere are server specs but embedded was the initial priority. I don't think there's been a lot of attention paid to desktop which isn't a super interesting area in general although it could of course piggyback on server work from a spec perspective if anyone were actually interested in giving it a go.
- mistrial9 4y ago> super interesting area in general deterred by the size of the profits for the winners, and the losses for those who do not compete in global markets.. yet I suggest there are few things more interesting than a personal, general purpose computer
- packetlost 4y agoWithout a company like Apple to put in the resources and engineering effort for something like Rosetta, there's really going to be next to no demand for a RISC-V based desktop computer outside of specialized development and maybe competing with ARM-based Chromebook-likes. Desktop systems are absolutely beholden to their platform and architecture because that's what determines which apps you can run. Any serious use of a desktop (that is not programming) basically needs to use Windows or Mac OS (think CAD, professional video editing, etc.) so you're not just convincing hardware manufacturers: you're convincing thousands of app vendors, and that's just not going to happen.
- dontlaugh 4y agoTrue. But I think more importantly, there will be no demand until someone makes a RISC-V CPU that can actually compete with Intel, AMD and Apple on performance.
- packetlost 4y agoI don't think that's necessarily a prerequisite. At least you could conceivably see demand for low-power, moderate performance Chromebook(-like) devices. For true desktop computing, yeah, I agree.
- worldofmatthew 4y agoA fees dollars saved from not paying ARM will guarantee adoption in low end laptops, tablets and smartphones. $100 Laptops, $70 phones and $50 tablets will be a big target for RISC-V.
- justahuman74 4y agoARM could just start price-matching the various RISC-V vendors, making themselves the easier choice due to the software ecosystem
- worldofmatthew 4y agoThey would have to offer the core for free to the SOC designers.
- humanwhosits 4y agoThe (good) riscv cores designs that implement the spec aren't free, it's the ISA spec that is free. There are some open source riscv cores, but the paid ones make money for a reason
- giantrobot 4y agoAll of those things you mention take advantage of the economies of scale of ARM production. They exist because a few years ago the basebands they're using were top of the line and were used in upmarket devices. They can buy an old baseband/board design, attach a screen and battery, and have a cheapo device for essentially zero development cost. If RISC-V doesn't see the development for upmarket products it's not going to magically take over the downmarket segments. No one footing the development bill is going to selling $50 tablets.
- cestith 4y agoIt's not the biggest subsegment of the desktop space, but there are a good number of people using Pi-level devices as a second desktop. RiscOS, Linux, NetBSD, and even Windows run on Raspberry Pi. Some of those run on several other similarly powered boards. In the open source space, plenty of apps already support AMD64, ARM32 and ARM64 and the distros distribute for them. If I can get Debian or Ubuntu on a system with even 1/10 the package repo of AMD64, it's worth considering for a cheap laptop or a small low-power desktop. Now I know that doesn't sound like much. Don't kid yourself into thinking Apple Silicon M1 and M2 came from nowhere, though. If it wasn't for growing capability in the ARM lines in other products Apple would not have been so likely to invest in it for their new technology, Rosetta or no. Exynos Chromebooks and such led the way to ARM Macbooks the same way the IBM PC led to displacing DEC and Sun workstations, then minicomputers, then x86 servers replacing most other servers in the DC.
- MobiusHorizons 4y ago> Exynos Chromebooks and such led the way to ARM Macbooks the same way the IBM PC led to displacing DEC and Sun workstations I think chrome books had very little to do with it. A lot of the work had already happened with the PowerPC switch. On the processor front, Apple’s arm processors aren’t at all like exynos chips that use standard arm cores. I would say that the apple silicon macs are more influenced by iPhone and iPad success than anything else, especially since iOS already runs a lot of macOS
- cestith 4y agoApple wouldn't have used ARM for the iPhone and iPad if the cores hadn't been proven in other similar platforms. ARM goes back a long time. My Psion palmtops have ARM cores. Many of the WinCE systems have ARM cores. The ARM processors in fact go back to 1985, with the ARM Development System for the BBC Micro and then the Archimedes in 1987. There's a whole world of ARM processors out there. The ISA, packaging, software, and expertise around it everywhere in the world helps make that ecosystem stronger. Before ARM there was Intel, and before Intel was PowerPC, yet even before that there were the 68000 series Macs. And before the Mac, there were the 65816 in the IIgs and the 6502 in the Apple II. Don't be surprised if Apple is an early adopter of RISC-V for support processors. If they decide they've made them performant enough after a few years of that, don't be surprised if they use them as CPUs and stop needing to license cores and ISAs from ARM at all. But I can promise you one thing. Apple didn't look at the 18 MHz v7 cores from Cirrus Logic in the Psion Series 5 and immediately decide they could make a mainstream desktop CPU out of it. The competition of companies like Samsung, Qualcomm, and Broadcom in consumer electronics has a lot to do with how ARM cores became suitable for Macbook.
- cpeterso 4y agoA good example was Windows NT. Over its lifetime, NT has supported Intel i860, x86, x86-64, Itanium, MIPS, Alpha, PowerPC, ARM, and ARM64. But today it only supports x86, x86-64, ARM, and ARM64. Alpha even had a Rosetta-like JIT to run x86 applications, though it was pretty slow.
- skybrian 4y agoOne datapoint: I don't know how popular OnShape is, but it seems to have a lot of features and I'm happy running CAD in a browser for hobbyist stuff.
- ephbit 4y ago> ... next to no demand for a RISC-V based desktop computer .. One thing that RISC-V enables is open source hardware CPUs. There are quite a few people who're upset by stuff like the Intel Management Engine IME making them distrust their personal computer. These folks don't really have any options that fit their criteria right now. Some RISC-V CPU could fit in there.
- loudmax 4y agoOver the next five? Probably not. But over ten or fifteen years? Very possibly. And if not porting apps directly to RISC-V, then porting them to WASM and letting browser vendors optimize WASM performance on RISC-V.
- vbezhenar 4y agoWhat's the difference between desktop and embedded? I reverse-engineered some medical device. It houses tiny CPU and 3" touch screen. Inside it runs Linux with X Window, Chromium, Electron and software written with JS. It's definitely embedded device, it's tiny, works from accumulator, hand-held. But its software stack is not any different from desktop.
- rowanG077 4y agoFor desktop you'd definitely want things like GPU and at least video decode. So that instantly makes it much more involved.
- notsapiensatall 4y agoTraditionally, the main difference was a full-featured MMU which allows virtual address spaces. But these days, you have advanced 600MHz microcontrollers with simple GPUs, and full-featured CPUs which get used as an embedded platform. You can even build a Linux kernel for no-MMU platforms. It's a fuzzy line.
- Symmetry 4y agoThe flexibility that makes RISC-V so compelling in embedded roles (what if I want 64 bit address but don't need hardware floating point?) makes it a harder target for the sort of workloads that you'd usually run on a server or desktop. If I were going to create an open high performance core to challenge x86 and ARM's A series cores I'd probably use PowerPC as a base rather than RISC-V. But I do think that RISC-V has a bright future in other segments.
- mixmastamyk 4y agoWhat are the trade-offs of PowerPC vs RISC-V?
- Symmetry 4y agoIn addition to RISC-V being more flexible than ideal here, PowerPC is more complicated as an instruction set which is a drawback if you're a student learning to implement your first processor or in a deeply embedded role. But given the huge amount of effort that goes into a high performance core it gets lost in the noise and it lets you execute tasks in fewer instructions without crazy difficult to implement levels of instruction fusion.
- brucehoult 4y agoRISC-V does not in any way depend on instruction fusion. I don't why this meme persists, especially as no RISC-V cores in the market do instruction fusion. High end OoO cores in other ISAs are BREAKING DOWN complex instructions into µops. RISC-V is pre-broken down. The one exception to that is current x86 and ARM cores DO do instruction fusion, to combine a compare with a following conditional branch. Which is a singe instruction in RISC-V in the first place. SO it is actually the other way around. Low end cores shouldn't be doing either fusion or breaking down into µops. They are supposed to be as simple as possible, and doing either of those is a complication using significant silicon area and energy. There might be a place for instruction fusion in mid-range cores. Things in the ARM Cortex A53 / A55 / A510 range. The most popular RISC-V core in that segment, the SiFive U74 (used in the HiFive Unmatched, BeagleV Starlight, VisionFive v1, VisionFive 2, Pine64 Star64 .. and probably more yet to be announced) doesn't fuse multiple instructions into one instruction, but it does pair a forward conditional branch past a single instruction with that following instruction. Both instructions still exist, they each go down one of the two execution pipelines side by side, the same as if the branch was predicted not-taken. At the final pipe stage if the branch turns out to be taken, instead of taking a mis-predicted branch penalty and flushing the pipeline, the U74 simply does not write the result of that following instruction back to the destination register. That's the closest any currently shipping RISC-V core I know of comes to instruction fusion. "crazy difficult to implement levels of instruction fusion" does not exist anywhere, and is not needed. It's just an idea from an academic which doesn't actually exist in the real world, at least at present.