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Why can't we have both? L4 cache anyone?
by d110af5ccf 4y ago
Why can't we have both? L4 cache anyone?
- adrian_b 4y agoThere are chances that in the future data centers the DIMM sockets from the CPU boards will be replaced by a combination of soldered DRAM on the CPU boards, for the lowest latency, combined with separate memory boards attached to the CPU through CXL links, for high capacity memories that can be allocated flexibly to the CPU boards, and that can be replaced or expanded independently of the CPUs.
- formerly_proven 4y agoIntel has already shown Sapphire Rapids samples with 64 GB of HBM 2e [1]. It's a safe bet that the HBM is not exclusive with external main memory. That'll be DDR5 of course, not CXL. Maybe in the 5th gen? [1] https://www.anandtech.com/show/17422/intel-showcases-sapphire-rapids-plus-hbm-xeon-performance-isc-2022 https://www.anandtech.com/show/17422/intel-showcases-sapphir...
- vimy 4y agoThat’s probably how the new M2 Mac Pro is going to work.
- ac29 4y agoM2 supports CXL?
- WithinReason 4y agoThis is what I was wondering. Or why isn't there something like a 2 GB HBM2 cache on GPUs? Is it cost or latency?
- mhh__ 4y agoIBM have been working with eDRAM in mainframes as cache, but mainframes and servers do different jobs.