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That would not solve much. Different types of transistors take different surface areas, so it would not prevent different companies using different references.

That would not solve much. Different types of transistors take different surface areas, so it would not prevent different companies using different references. Also, they can very well have a high-density library for benchmarks that can be quite different from what they can do when they actually need the thing to work. The solution is simple: treat their numbers as brands. A Core i9 is generally better than an i3 of the same generation, but where a Ryzen 5 is compared to that is anyone’s guess (depends on the exact models, generations, etc). Node sizes have had nothing to do with a characteristic length for quite a while now, that ship has sailed.

amelius 4y ago
FLOPS/mm^2 perhaps? Where 1 FLOP is a multiplication of two 128bit operands? Implemented however the foundry would like.
- kergonath 4y ago
  Even if it were practical, the question remains: why would they do that? The only people upset with this are benchmark warriors. People in the industry or familiar enough know how to navigate the characteristics of a process and do not need one single neat number. Customers by and large don’t care: business are after the cheapest and best supported, and consumers are mostly price-sensitive except for higher-end brands that don’t communicate at all on this sort of things. This would not solve any of the industry’s problems.
- sroussey 4y ago
  They sorta have these things, but no one looks at it. For example the scaling factor from from say 5nm to 3nm for transitory is X. But for SRAM, things have been getting progressively worse so it often X/2. And with caches going up you end up using a process node terrible for sram, but needed for cpu transistors, and it’s a huge waste. You can see why you might use a different process tech for caches, and AMD is clearly going this direction. Anyhow, TMSC 3nm is just a marketing term. On the physics side, it has about 7-8 key differences to previous 5nm. That’s 6-7 too many things for people to care or remember about. Intel used to use a part of the transistor when it takes about scale. But then the geometry of the transistor changed! That number no longer has meaning. And transistor geometry changes over time, and you have multiple to choose from on the same process node. Oops. So… back to marketing terms.

amelius 4y ago

FLOPS/mm^2 perhaps? Where 1 FLOP is a multiplication of two 128bit operands? Implemented however the foundry would like.

kergonath 4y ago
Even if it were practical, the question remains: why would they do that? The only people upset with this are benchmark warriors. People in the industry or familiar enough know how to navigate the characteristics of a process and do not need one single neat number. Customers by and large don’t care: business are after the cheapest and best supported, and consumers are mostly price-sensitive except for higher-end brands that don’t communicate at all on this sort of things. This would not solve any of the industry’s problems.
sroussey 4y ago
They sorta have these things, but no one looks at it. For example the scaling factor from from say 5nm to 3nm for transitory is X. But for SRAM, things have been getting progressively worse so it often X/2. And with caches going up you end up using a process node terrible for sram, but needed for cpu transistors, and it’s a huge waste. You can see why you might use a different process tech for caches, and AMD is clearly going this direction. Anyhow, TMSC 3nm is just a marketing term. On the physics side, it has about 7-8 key differences to previous 5nm. That’s 6-7 too many things for people to care or remember about. Intel used to use a part of the transistor when it takes about scale. But then the geometry of the transistor changed! That number no longer has meaning. And transistor geometry changes over time, and you have multiple to choose from on the same process node. Oops. So… back to marketing terms.