6 ms·

This suggests another way forward: Re-encode the existing opcodes with new, more regular byte sequences. E.g. 32 bits / instruction, with some escape for e.g.

This suggests another way forward: Re-encode the existing opcodes with new, more regular byte sequences. E.g. 32 bits / instruction, with some escape for e.g. 64bit constants. You'll have to redo the backend of the assembler, but most of the compiler and optimization wisdom can be reused as-is. Of course, this breaks backward compatibility completely so the high performance mode can only be unlocked for recompiles.

colejohnson66 4y ago
That was Itanium, and it failed for a variety of reasons; one of which was a compatibility layer that sucked. You can't get rid of x86's backwards compatibility. Intel and AMD have done their best by using vector prefixes (like VEX and EVEX)[a] that massively simplify decoding, but there's only so much that can be done. People get caught up in the variable length issue that x86 has, and then claim that M1 beats x86 because of that. Sure, decoding ARM instructions is easier than x86, but the variable length aspect is handled in the predecode/cache stage, not the actual decoder. The decoder, when it reaches an instruction, already knows various bits of info are. The RISC vs CISC debate is useless today. M1's big advantage comes from the memory ordering model (and other things)[0], not the instruction format. Apple actually had to create a special mode for the M1 (for Rosetta 2) that enforces the x86 ordering model (TSO with load forwarding), and native performance is slightly worse when doing so. [0]: https://twitter.com/ErrataRob/status/1331735383193903104 https://twitter.com/ErrataRob/status/1331735383193903104 [a]: There's also others that predate AVX (VEX) such as the 0F38 prefix group consisting only of opcodes that have a ModR/M byte and no immediate, and the 0F3A prefix being the same, but with an 8 bit immediate.
- kmeisthax 4y ago
  M1 doesn't have a special mode for Rosetta. All code is executed with x86 TSO on M1's application processors. How do I know this? Well, did you know Apple ported Rosetta 2 to Linux? You can get it by running a Linux VM on macOS. It does not require any kernel changes to support in VMs, and if you extract the binary to run it on Asahi Linux, it works just fine too. None of the Asahi team did anything to support x86 TSO. Rosetta also works just fine in m1n1's hypervisor mode, which exists specifically to log all hardware access to detect these sorts of things. If there is a hardware toggle for TSO, it's either part of the chicken bits (and thus enabled all the time anyway) or turned on by iBoot (and thus enabled before any user code runs). Related point: Hector Martin just upstreamed a patch to Linux that fixes a memory ordering bug in workqueues that's been around since before Linux had Git history. He also found a bug in some ARM litmus tests that he was using to validate whether or not they were implemented correctly. Both of those happened purely because M1 and M2 are so hilariously wide and speculative that they trigger memory reorders no other CPU would.
  - anyfoo 4y ago
    > M1 doesn't have a special mode for Rosetta. All code is executed with x86 TSO on M1's application processors. That's not true. (And doesn't your last paragraph contradict it already?) You might just have figured out that most stuff will run fine (or appear to run fine for a long time) when TSO isn't enabled.
    - messe 4y ago
      I have no idea why you are being downvoted. You are entirely correct.
      - anyfoo 4y ago
        Thanks, I was puzzled as well. The downvotes seem to have stopped, though.
  - messe 4y ago
    I'm sorry, but please cite some sources, because this contradicts everything that's been said about M1's x86 emulation that I've read so far. > Well, did you know Apple ported Rosetta 2 to Linux? You can get it by running a Linux VM on macOS. It does not require any kernel changes to support in VMs, and if you extract the binary to run it on Asahi Linux, it works just fine too. None of the Asahi team did anything to support x86 TSO. Rosetta also works just fine in m1n1's hypervisor mode, which exists specifically to log all hardware access to detect these sorts of things. If there is a hardware toggle for TSO, it's either part of the chicken bits (and thus enabled all the time anyway) or turned on by iBoot (and thus enabled before any user code runs). Apple tells you to attach a special volume/FS to your linux VM in order for Rosetta to work. When such a volume is attached, it runs the VM in TSO mode. As simple as that. The rosetta binary itself doesn't know whether or not TSO is enabled, so its not surprising that it runs fine under Asahi. As marcan42 himself said on twitter[1], most x86 applications will run fine even without TSO enabled. You're liable to run into edge cases in heavily multithreaded code though. [1]: https://twitter.com/marcan42/status/1534054757421432833 https://twitter.com/marcan42/status/1534054757421432833 > Both of those happened purely because M1 and M2 are so hilariously wide and speculative that they trigger memory reorders no other CPU would. In other words, they're not constantly running in TSO mode? Because if they were, why would they trigger such re-orders? EDIT: I've just run a modified version of the following test program[2] (removing the references to the tso_enable sysctl which requires an extension), both native and under Rosetta. Running natively, it fails after ~3500 iterations. Under Rosetta, it completes the entire test successfully. [2] https://github.com/losfair/tsotest/ https://github.com/losfair/tsotest/
- ShroudedNight 4y ago
  I thought the critical failure of Itanium was that a priori VLIW scheduling turned out to be a non-starter, at least as far as doing so efficiently
  - atq2119 4y ago
    The entire approach is misguided for single-threaded performance. It turns out that out-of-order execution is pretty important for a number is things, perhaps most importantly dealing with variable memory instruction latencies (cache hits at various points in the hierarchy vs. misses). A compiler simply cannot statically predict those well enough.
- Dylan16807 4y ago
  > That was Itanium What? No. Itanium was a vastly, wildly different architecture.
- FullyFunctional 4y ago
  Two factual mistakes: * IA-64 failed primarily because it failed to deliver the promised performance. x86 comparability isn't and wasn't essential to success (behold the success on Arm for example). * M1's advantage has almost nothing to do with the weak memory model, but it has to do with everything: wider, deeper, faster (memory). The ISA being Arm64 also help in many ways. The variable length x86 instructions can be dealt with via predecoding, sure to an extent, but that lengthens the pipeline which hurts the branch mispredict penalty, which absolutely matters.
- hyperman1 4y ago
  Think more of a re-encoding than a full re-architecture. Every existing 16/32/64 bit instruction should receive some place in that re-encoded opcode map, including abominations as aaa. But e.g the whole prefix thing should go away. The processor's predecode stage should cease existing. Let's roughly sketch a proposal, even if many variants are possible Instructions start on 64 bit boundarys. If the highest bit is 0 you have an insn else a constant. So the whole thing becomes self-synchronizing. You're now of course missing 1 bit, that should get a place in the encoding of a constant. This means you have 62 bits left. Presuming the prefixes like segment regs get solved, you could encode 2 instructions in there, 1 of them a nop if you need the constant. Do away with short encodings for ax. Try and avoid double encodings uf reg + modrm combos exist. Above all, resist the temptation to mess with the instruction set, just re encode.
School-Cotton 4y ago
If you're inventing a completely incompatible ISA, why not just use ARM64 at that point?
- anamax 4y ago
  Perhaps because you don't want to commit to ARM compatiblity AND licensing fees.
  - yjftsjthsd-h 4y ago
    Alright, then RISC-V?
hakfoo 4y ago
I always wondered if there was a case to be made for a JIT that recompiled "normal" x86-64 into a restricted subset designed to be more optimizable. This could be paired with a sort of two-tiered processor design-- really fast on the restricted subset, but mediocre-to-bad performance on anything else. The code only has to activate the "mediocre to bad" paths long enough to build a JIT cache though,
- deleted 4y ago
  [deleted]
- therealcamino 4y ago
  That's sort of similar to Transmeta's approach, except the underlying machine was pretty different from x86, not a fast subset.

colejohnson66 4y ago

That was Itanium, and it failed for a variety of reasons; one of which was a compatibility layer that sucked. You can't get rid of x86's backwards compatibility. Intel and AMD have done their best by using vector prefixes (like VEX and EVEX)[a] that massively simplify decoding, but there's only so much that can be done. People get caught up in the variable length issue that x86 has, and then claim that M1 beats x86 because of that. Sure, decoding ARM instructions is easier than x86, but the variable length aspect is handled in the predecode/cache stage, not the actual decoder. The decoder, when it reaches an instruction, already knows various bits of info are. The RISC vs CISC debate is useless today. M1's big advantage comes from the memory ordering model (and other things)[0], not the instruction format. Apple actually had to create a special mode for the M1 (for Rosetta 2) that enforces the x86 ordering model (TSO with load forwarding), and native performance is slightly worse when doing so. [0]: https://twitter.com/ErrataRob/status/1331735383193903104 https://twitter.com/ErrataRob/status/1331735383193903104 [a]: There's also others that predate AVX (VEX) such as the 0F38 prefix group consisting only of opcodes that have a ModR/M byte and no immediate, and the 0F3A prefix being the same, but with an 8 bit immediate.

kmeisthax 4y ago
M1 doesn't have a special mode for Rosetta. All code is executed with x86 TSO on M1's application processors. How do I know this? Well, did you know Apple ported Rosetta 2 to Linux? You can get it by running a Linux VM on macOS. It does not require any kernel changes to support in VMs, and if you extract the binary to run it on Asahi Linux, it works just fine too. None of the Asahi team did anything to support x86 TSO. Rosetta also works just fine in m1n1's hypervisor mode, which exists specifically to log all hardware access to detect these sorts of things. If there is a hardware toggle for TSO, it's either part of the chicken bits (and thus enabled all the time anyway) or turned on by iBoot (and thus enabled before any user code runs). Related point: Hector Martin just upstreamed a patch to Linux that fixes a memory ordering bug in workqueues that's been around since before Linux had Git history. He also found a bug in some ARM litmus tests that he was using to validate whether or not they were implemented correctly. Both of those happened purely because M1 and M2 are so hilariously wide and speculative that they trigger memory reorders no other CPU would.
- anyfoo 4y ago
  > M1 doesn't have a special mode for Rosetta. All code is executed with x86 TSO on M1's application processors. That's not true. (And doesn't your last paragraph contradict it already?) You might just have figured out that most stuff will run fine (or appear to run fine for a long time) when TSO isn't enabled.
  - messe 4y ago
    I have no idea why you are being downvoted. You are entirely correct.
    - anyfoo 4y ago
      Thanks, I was puzzled as well. The downvotes seem to have stopped, though.
- messe 4y ago
  I'm sorry, but please cite some sources, because this contradicts everything that's been said about M1's x86 emulation that I've read so far. > Well, did you know Apple ported Rosetta 2 to Linux? You can get it by running a Linux VM on macOS. It does not require any kernel changes to support in VMs, and if you extract the binary to run it on Asahi Linux, it works just fine too. None of the Asahi team did anything to support x86 TSO. Rosetta also works just fine in m1n1's hypervisor mode, which exists specifically to log all hardware access to detect these sorts of things. If there is a hardware toggle for TSO, it's either part of the chicken bits (and thus enabled all the time anyway) or turned on by iBoot (and thus enabled before any user code runs). Apple tells you to attach a special volume/FS to your linux VM in order for Rosetta to work. When such a volume is attached, it runs the VM in TSO mode. As simple as that. The rosetta binary itself doesn't know whether or not TSO is enabled, so its not surprising that it runs fine under Asahi. As marcan42 himself said on twitter[1], most x86 applications will run fine even without TSO enabled. You're liable to run into edge cases in heavily multithreaded code though. [1]: https://twitter.com/marcan42/status/1534054757421432833 https://twitter.com/marcan42/status/1534054757421432833 > Both of those happened purely because M1 and M2 are so hilariously wide and speculative that they trigger memory reorders no other CPU would. In other words, they're not constantly running in TSO mode? Because if they were, why would they trigger such re-orders? EDIT: I've just run a modified version of the following test program[2] (removing the references to the tso_enable sysctl which requires an extension), both native and under Rosetta. Running natively, it fails after ~3500 iterations. Under Rosetta, it completes the entire test successfully. [2] https://github.com/losfair/tsotest/ https://github.com/losfair/tsotest/
ShroudedNight 4y ago
I thought the critical failure of Itanium was that a priori VLIW scheduling turned out to be a non-starter, at least as far as doing so efficiently
- atq2119 4y ago
  The entire approach is misguided for single-threaded performance. It turns out that out-of-order execution is pretty important for a number is things, perhaps most importantly dealing with variable memory instruction latencies (cache hits at various points in the hierarchy vs. misses). A compiler simply cannot statically predict those well enough.
Dylan16807 4y ago
> That was Itanium What? No. Itanium was a vastly, wildly different architecture.
FullyFunctional 4y ago
Two factual mistakes: * IA-64 failed primarily because it failed to deliver the promised performance. x86 comparability isn't and wasn't essential to success (behold the success on Arm for example). * M1's advantage has almost nothing to do with the weak memory model, but it has to do with everything: wider, deeper, faster (memory). The ISA being Arm64 also help in many ways. The variable length x86 instructions can be dealt with via predecoding, sure to an extent, but that lengthens the pipeline which hurts the branch mispredict penalty, which absolutely matters.
hyperman1 4y ago
Think more of a re-encoding than a full re-architecture. Every existing 16/32/64 bit instruction should receive some place in that re-encoded opcode map, including abominations as aaa. But e.g the whole prefix thing should go away. The processor's predecode stage should cease existing. Let's roughly sketch a proposal, even if many variants are possible Instructions start on 64 bit boundarys. If the highest bit is 0 you have an insn else a constant. So the whole thing becomes self-synchronizing. You're now of course missing 1 bit, that should get a place in the encoding of a constant. This means you have 62 bits left. Presuming the prefixes like segment regs get solved, you could encode 2 instructions in there, 1 of them a nop if you need the constant. Do away with short encodings for ax. Try and avoid double encodings uf reg + modrm combos exist. Above all, resist the temptation to mess with the instruction set, just re encode.

School-Cotton 4y ago

If you're inventing a completely incompatible ISA, why not just use ARM64 at that point?

anamax 4y ago
Perhaps because you don't want to commit to ARM compatiblity AND licensing fees.
- yjftsjthsd-h 4y ago
  Alright, then RISC-V?

hakfoo 4y ago

I always wondered if there was a case to be made for a JIT that recompiled "normal" x86-64 into a restricted subset designed to be more optimizable. This could be paired with a sort of two-tiered processor design-- really fast on the restricted subset, but mediocre-to-bad performance on anything else. The code only has to activate the "mediocre to bad" paths long enough to build a JIT cache though,

deleted 4y ago
[deleted]
therealcamino 4y ago
That's sort of similar to Transmeta's approach, except the underlying machine was pretty different from x86, not a fast subset.