6 ms·
Standard reminder: The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate le
by Jabbles 4y ago
Standard reminder:
The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the semiconductor chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.
https://en.wikipedia.org/wiki/2_nm_process https://en.wikipedia.org/wiki/2_nm_process
- joemi 4y agoIs there a meaningful metric that changes between generations, that could alternatively be used, perhaps by consumers in spite of marketing's desires?
- nabla9 4y agoYes. The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count. Transistor count/area = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area
- bpodgursky 4y agoThat's disappointing I always liked to believe that when two fourth-generation fighters fell in love, they produced an F-35.
- umvi 4y agoI hate that that's legal. Imagine if the food industry could get away with this in their marketing: "10g Fiber Bars" (fiber bars actually contain only 1g of fiber, "10g fiber" just refers to the fact that it's the 10th generation of fiber bar they've created)
- jjoonathan 4y agoOh yeah? But my fiber bars are Asbestos Free! (thanks XKCD, I hate whoever figured this out too)
- mortenjorck 4y agoLike household products marketed as "not tested on animals" when all the compounds in the product were already tested on animals a century ago and the overhead for using any novel compounds would mean a vastly higher price (and probably animal testing).
- wahern 4y agoGypsum water is a thing: https://en.wikipedia.org/wiki/Three_Legs_Cooling_Water https://en.wikipedia.org/wiki/Three_Legs_Cooling_Water I've been given this as a treatment for a cold/flu. I drank it (didn't want to be rude) but couldn't stop thinking about how gypsum used to sometimes be contaminated with asbestos (due to coming from the same mines, I think, long ago).
- audunw 4y agoWhy do you care what the minimum gate length is of a process? Do you design standard cell libraries? Transistor density is the only thing you actually care about, and they've continued decreasing the numbers to roughly match what you'd expect from the "nm" number with old planar transistors. The comparison to a "10g fiber bar" doesn't work, because in the case of semiconductors the "10g fiber bar" is 10 times better than a "1g fiber bar" TSMC has sometimes started to use eg. N7 instead of 7nm.. but it really doesn't matter.
- umvi 4y agoI don't necessarily care what the minimum gate length is. But I don't like misleading marketing terms that ostensibly give you information about the product, but in reality don't give you any information at all. If marketing wants to use some metric to convey how good the product is, that's fine, but if the only information being conveyed is the product generation number, they should not be able to masquerade that generation number as a metric. Otherwise it misleads consumers into thinking, i.e. "2nm chips should be able to contain twice as many transistors as 4nm chips!" when that is false.
- adrian_b 4y agoActually "2 nm" chips are supposed to have 4 times more transistors than "4 nm" chips, because the area scales like the square of the length. Because each process generation was supposed to double the transistor density, the names of the processes have been given to correspond approximately with a geometric progression having the ratio sqrt(2): 500 nm, 350 nm, 250 nm, 180 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, ... , but then the need to round to integer numbers combined with the desire to give distinct names to some process variants that have only small changes in the transistor density (e.g. "6 nm" vs. "7 nm") have lead to deviations from the original progression. While the transistor density has increased with each process generation, most recent generations have been content with a less than double density, e.g. with a density 1.8 times greater than in the previous generation.
- throw827474737 4y agoIf it doesn't matter why cant they just switch to a density number that translates better than a lookup table and doesn't refer to a measure it has no relationship with anymore?
- skybrian 4y agoI don't think any consumer products get advertised this way? "Now with 2-nm technology inside" is not something anyone cares about. It's not a meaningful benchmark for a chip. The companies that contract with chip foundries probably know what they're getting. It makes reading industry news a bit more confusing, but for most of us, we're reading it for entertainment, not any practical purpose.
- whiteboardr 4y agoFar less annoying and above all far less dangerous than allowing a car company to call their half-baked solution “Auto Pilot”.
- deleted 4y ago[deleted]
- bluedino 4y ago> "10g Fiber Bars" (fiber bars actually contain only 1g of fiber The supplement industry is good at this. You might see a protein bar with 30g of protein, and find out it's just amino spiking[1] People in the fitness industry were sending products into labs to have them analyzed and then exposing the companies on YouTube. [1]:The act of using low grade amino acids (usually L-Taurine and/or L-Glycine) to bump up the overall protein content
- Judson 4y agoSimilarly as a kid, I was surprised to learn "One-hour Photo" was a brand and didn't necessarily mean your photos would be ready in one hour...
- option 4y agoyou might be interested why sugar contents is never mentioned as % of daily norm on food packaging in US
- Symmetry 4y agoIt's less that they're marketing deceptively than that the measure they were using stopped making sense. If the ITRS back in the day had known we'd stop using planar transistors they could have named their nodes for the transistor density they achieved but they didn't and so we're stuck with a naming convention that no longer refers to a real physical quantity but we are still getting the density improvements per node that we traditionally have.
- zaptrem 4y agoWhy don't we just switch to that now?
- Symmetry 4y agoDecades of tradition. And it's not clear exactly what they would switch to, in general transistors double every node but different processes tend to have different design rules so different processes might give you different densities on different designs making the exact reference design a fraught question.
- smiley1437 4y agoLooking forward to negative nanometer processes in the future
- gonehome 4y agoYeah I’m also wondering what’s going to happen at that point.
- umvi 4y agoMost likely they'll just switch to picometers, then femtometers, etc, each one yielding 10 generations or so
- not2b 4y agoIn a silicon crystal, the minimum distance between atoms is 0.235nm. So, no.
- jbverschoor 4y agoIn marketing, anything is possible
- gonehome 4y agoYeah we’ve already entered marketing land when it comes to this years ago.
- mqus 4y agoI think the most realistic guess would probably be a switch to some different nomenclature like G1, G2, G3 etc for generations or literally anything else like product lines (see what happened to nvidias/amds graphics card numbering, etc)
- ge96 4y agoWeren't "3D chips" a thing? Did that take off/used anywhere. Sounded like a big deal along with the idea of smaller = better.
- dragonelite 4y agoYou're still limited to thermal and cooling capacity if im not mistaken.
- iasay 4y agoYes it’s used in FLASH now. Look up 3D NAND. It’s mostly hopeless for compute though because it’s difficult getting rid of the heat.
- mook 4y agoThere's "3D V-cache" now too (cache on top of compute, or something along those lines).
- audunw 4y agoTransistors are more "3D" now, that's why a 10nm process gives you something like the same density as what a 2D planar transistor with 10nm minimum gate length would. See "FinFET" or "GAA" transistors If you're talking about stacking entire chips, yes that's also used lots of places. The challenge there is getting rid of the heat from those chips. If you stack lots of chips it gets really hard to get heat out of the ones in the middle.
- tonmoy 4y agoIf you are referring to 3D devices like FinFET then they are absolutely a thing and is being used pretty widely. If you are referring to stacking devices in 3D space then the power density becomes too much and it becomes impractical
- standardUser 4y agoThe fact that is is shorthand for "increased speed and reduced power consumption" seems to make it a perfect metric for comparing chips, especially for those of us who have zero interest in learning more than one metric to compare chips (almost everyone).
- anonymoose42 4y ago
- nsxwolf 4y agoSo how many nanometers is the smallest physical feature now?
- wetpaws 4y agoVaries from fab to fab.
- mrep 4y agoMore like varies from marketing department to marketing department.
- adrian_b 4y agoThe dimensions that matter are the pitches of the transistors (i.e. of their gates) and of the first layer of metal interconnections, because these are the dimensions which determine the size of a logical gate or of a memory cell. For state-of-the-art CMOS processes, these pitches are in the range 30 nm ... 50 nm. See for example the table "Comparing Intel 4 to Intel 7", at: https://www.anandtech.com/show/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance https://www.anandtech.com/show/17448/intel-4-process-node-in...
- samatman 4y agoYeah, it's annoying, but you can see how it happened: the nomenclature was accurate from 10µm to 32nm, and became marketing rather than measurement slowly, not all at once. The choices are rename everything in the past according to a new objective standard (impractical), make a clean break and use a new objective standard (but what?), or just let 'nm' become some rough and increasingly useless way of indicating die density, where lower is better. So that's what happened.
- not2b 4y agoUp until about 2003 or so, scaling worked near-perfectly, so geometries were essentially the same from generation to generation. This meant that one number, describing minimum feature size, told you what you needed to know. Eventually leakage current became a major issue, so fabs had to do major redesign and change the shapes of the transistors, and different foundries did this differently so that minimum feature length is no longer directly comparable. You can still compare density: how many transistors or gates in a given area.
- scrlk 4y ago> You can still compare density: how many transistors or gates in a given area. I would say that comparing density comes with its own caveats. E.g. SRAM is denser than logic, so a chip with a lot of cache could skew a density metric. I guess for a true "apples to apples comparison" of processes you'd want to implement the same design on separate nodes with a mixture of SRAM & logic. Are there any reference designs used for this?
- unethical_ban 4y agoWhy is it impractical? I know nothing about CPU architecture. Clearly we aren't measuring performance with x-nm terminology, but the manufacturing process. Can we not use transistor density per mm^2, or if 3-dimensional, by mm^3?
- nabla9 4y agoThose names are relevant in planar processes (32 nm was last planar prosess for Intel). With FinFets, Gate-All-Around, ribbon fet etc. that makes no sense. The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count. Transistor count = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area
- peter_retief 4y agoThat seems very disingenuous and disappointing!