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Yes, the RISC-V AIA has been a standard for some months now.
by bonzini 4y ago
Yes, the RISC-V AIA has been a standard for some months now.
- phendrenad2 4y agoOut of curiosity, if anyone can answer: There are many RISC-V CPU cores. Are there implementations of full systems, including PCI-E host, on an FPGA platform?
- p_l 4y agoThe article seems to claim that AIA is still a work-in-progress thing?
- pavehawk2007 4y agoAIA is still a work in progress. The last draft release was 18 days ago, and it is at version 0.3.0-31. Verify here: https://github.com/riscv/riscv-aia/releases https://github.com/riscv/riscv-aia/releases As the article mentions, there was a major change between 30 and 31 where the SETEIENUM/SETEIPNUM as well as the CLREIENUM/CLREIPNUM CSRs were removed. The issue on GitHub reads that they were removed since the architecture review board asked for them to be removed. A manufacturer can use a draft spec, but it may be rendered outdated sooner rather than later.
- eqvinox 4y agoThat is shockingly young, like the GP I had assumed MSI would've been designed in when the PLIC was designed (i.e. ≤ 2019). The PLIC doc says something about "Interrupt Gateways", did those not make it?